Tool/software:
We are trying to access CC1311P3 chip using code composer studio in the debug mode but we are getting "cant run target cpu error -2134". We are able to do debugging with launchpad with the same project source code,
Please let us know if we need to anything differently for the On-Chip device.
I am sorry, but I do not understand what you are asking.
Have you made your own HW and are not able to debug/download code, while you can with the LP?
What is the "On-Chip Device"?
If you have made your own HW, what reference design have you used?
Also specify which SDK version you are using, what example you are trying to debug, and which tools (and version you are using)
Siri
Its our own HW and We have followed the CC1311 reference design (LAUNCHXL-CC1352P-4). We made a customization by removing the onboard MCU(MSP432E401YTPDT), its circuits and we have given CC1311 JTAG to header directly. Other circuits are same as reference.
Tool Used: Code composer Studio v12
SDK Version: simplelink_cc13xx_cc26xx_sdk_7_41_00_17
We have enabled "Force VDDR" in the device configuration of the example project "uart2echo_LP_CC1311P3_freertos_gcc". With this setting, we were able to fix the above mentioned issue.
Please help us understand how this could impact and also confirm if this configuration is expected.
Hi, Please let us know the impact of Force VDDR as mentioned in the above query.
Also we are planning to use the following configurations with CC1311P3. Please let us know the RF configurable options available for the same.
FEC: 1/2 rate convolutional coding
Preamble (4 bytes): AAAAAAAA
Sync Word (4 bytes): 91D391D3
Whitening : Enabled as in CC1110
Deviation: 3.707866 kHz
Channel spacing: 363372.8027
Manchester Encoding : Disabled
Modulation: 2-FSK
Center Frequency : 400.2 MHz and 450.1 MHz
IF Frequency : 158.203 kHz
Frequency Offset : 0
Hi,
Changing the VDDR should not impact the debug capabilities. It could be that your VDDR is just on the limit of a threshold and forcing VDDR can be resolving this by increasing VDDR.
Do you have any external circuitry connected to VDDR in your design ?
Hi RGW,
We don't have any external circuit, its connected to the IC DCDC, as per the reference schematic.
Can you also please check and comment on the below configuration possibility in CC1311.
FEC: 1/2 rate convolutional coding
Preamble (4 bytes): AAAAAAAA
Sync Word (4 bytes): 91D391D3
Whitening : Enabled as in CC1110
Deviation: 3.707866 kHz
Channel spacing: 363372.8027
Manchester Encoding : Disabled
Modulation: 2-FSK
Center Frequency : 400.2 MHz and 450.1 MHz
IF Frequency : 158.203 kHz
Frequency Offset : 0
Thanks,
Theiv