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CC1101 layout on a multilayer pcb

Robin Venables1
Prodigy 20 points
Other Parts Discussed in Thread: CC1101

I am laying out the CC1101 reference design on a 1.6 mm multilayer PCB. My previous experience is on 0.8 mm double-sided PCB. In the region of the CC1101, I have designated both internal layers as ground planes, with good stitching between the two. There is only 0.1 mm between the RF routing layer and the upper ground plane, leading to excessive capacitance on the SMD pads. If I clear this plane and use the other internal layer as ground, the distance is 1.2 mm, which is greater than the 0.8 mm of the reference design. Intuition tells me that the circuit will be happier with the upper layer as ground but how do I mitigate the pad capacitance? Is it OK to put holes in the upper ground plane under the pads to reduce the capacitance?

  • 0
    TI__Guru**** 317180 points
    Why have you chosen a stack-up with so short distance between the signal layer and the first ground layer?

    I find it difficult to comment on what would be better.
    Option 1: Inner layer 1 used as ground. This means large parasitics and the matching should probably be adjusted to take this into account. But which components and by how much is difficult to say since we haven't done any ref design with this stack-up
    Option 2: Inner layer 2 used as ground. The inductance in the vias from the ground pad of the chip to the ground plane will be larger than in the ref design. I think this will have limited negative impact. One option is to have inner layer 1 as ground just user the chip but not user the RF network.

    If you have access to ADS I would have run some simulations to check how the impedance change compared to the ref design with the different options.
  • 0 in reply to TER
    Prodigy 20 points
    Thank you.
    The stack-up is default for 4-layer and by far the cheapest but yes, one option is to propose that the two inner layers are the close-together ones. I don't have access to RF simulation tools. I like your idea of using inner layer one under the chip, which suggests that I simply remove inner layer 1 from the whole of the balun and antenna matching area. I need to be careful to stitch the two inner layers together round the perimeter of the cut-out. Your feedback about the relatively minor impact of the increased inductance of the vias with the more distant plane over the increased capacitance of the pads with the nearer plane is exactly the insight I was after.