Sirs:
We are using sniff mode to minimize receive power consumption but we have some older systems that output minimal preamble length. One system appears to produce only 10 bit preamble bits ahead of the 11 bit sync which also contains 9 bits of preamble (that don't count as preamble bits). So the sniff must be designed to detect short preambles.
Our system uses an ext 40Mhz tcxo. So I'm able to measure sniff duty cycles directly by monitoring pin 29 ( DCPL_XOSC) which is being used to power up the XOSC during sniffing.
Used the xcel spreadsheet, CC120X_SniffMode.xlxs to calculate tevent0 in ms and the hex configuration setting. Used the config setting to set up and operate the chip in sniff mode and then measure the XOSC powering voltage with an oscilloscope.
Following are the measurements:
Pream bytes Event0 Width p29 Tevent0calc Tevent0meas
.5 00 00 6.6 ms 0 9.52 ms
1.0 00 85 6.37 ms 3.33 6.6 ms
2.0 01 8F 6.87 ms 9.99 ms 9.99 ms
3.0 02 9A 6.48 ms 16.65 ms 16.61 ms
4.0 03 A4 6.56 ms 23.31 ms 23.36 ms
This data agrees with calculations for preamble bytes 2, 3, and 4 and above. But for 0.5 preamble bytes the duty cycle should be 100% but the data appears to have taken a wrong turn.
Same with 1 preamble byte which should be nearly 100%. Did notice that Sync_CFGx.pqt_gating =1 which is not recommended.
So I must be missing something in my config which probably an expert can spot immediately. The config follows:
/***************************************************
150Mhz Sniff mode GPIO0 not pulsing
Rx filter=19.84khz, 2 GFSk, 2.68k dev, 2.4kbps
sync= 05,56 doesn't include type
11bits ,no seq no, fixed 3 byte 0bit
7 byte preamble Sends to MCDT rec and ti rec
TI receiver evb: RF current=5.4ma, mcu current=2.6ma
****************************************************/
const registerSetting_t preferredSettings[]=
{
//{CC120X_IOCFG3, 0x3c}, //dec 60. read ext osc enable. Doesn't work
{CC120X_IOCFG2, 0x06}, //sniff 150M
//{CC120X_IOCFG1, 0x00}, //make GPIO1 output & invert to high (see 3.4)
{CC120X_IOCFG0, 0x06},
{CC120X_SYNC3, 0x55}, //was AA, 55 7:0 sets MSB sync. AA for inverted
{CC120X_SYNC2, 0x55}, //was AA, 55, 7:0 sets MSB sync.
{CC120X_SYNC1, 0x55}, //was AA, 55, 05 7:0 sets MSB sync.
{CC120X_SYNC0, 0x56}, //was A9, 56 sets lsb of sync in 7:0. Orig A6
{CC120X_SYNC_CFG0, 0x88}, //was 88. added PQT_EN & PQT_Gating_En, strict_sync_check=3
{CC120X_SYNC_CFG1, 0x28}, //28=11 bits & 8 thresh. was 48. 4x=16bits, 8x=24bits, Ax=32 bits 7-5 len sync, 4:0=sync thresh
{CC120X_DEVIATION_M, 0x8D},
{CC120X_MODCFG_DEV_E, 0x08},
{CC120X_DCFILT_CFG, 0x5D},
{CC120X_PREAMBLE_CFG1, 0x14}, //14=3bytes, 18=4b. 10=2bytes e AA. was 24. 0x31=24bytes. 0x25=7bytes
{CC120X_PREAMBLE_CFG0, 0x8A},
{CC120X_IQIC, 0xCB},
{CC120X_CHAN_BW, 0xAC}, //AC=9.46khz. AA=10khz
{CC120X_MDMCFG1, 0x60}, //40=fifo en, Man mode=20, invert data=10
{CC120X_MDMCFG0, 0x05},
{CC120X_SYMBOL_RATE2, 0x4F},
{CC120X_SYMBOL_RATE1, 0x75},
{CC120X_SYMBOL_RATE0, 0x10},
{CC120X_AGC_REF, 0x31},
{CC120X_AGC_CS_THR, 0x09},
{CC120X_AGC_CFG1, 0x40},
//{CC120X_AGC_GAIN_ADJUST, 0xAC}, //-84
{CC120X_AGC_CFG0, 0x87}, //2counts for rssi
{CC120X_FIFO_CFG, 0x00},
{CC120X_SETTLING_CFG, 0x03},
{CC120X_FS_CFG, 0x1B},
{CC120X_WOR_CFG0, 0x08}, //same
{CC120X_WOR_CFG1, 0x08}, //added
{CC120X_WOR_EVENT0_MSB, 0x00}, //02, 3B pre. was 01. was 02
{CC120X_WOR_EVENT0_LSB, 0x00}, //9a, 3b pre. was 8f for 2bytws. was e2
{CC120X_PKT_CFG2, 0x00}, //norm mode, CRc disabled, no status byte
{CC120X_PKT_CFG1, 0x00}, // 0x01=append RSSI. Adx check & crc disabled. This line needed to rec MCDT!
{CC120X_PKT_CFG0, 0x10}, //x18 pro 6bits, x10 EMIDS 4bits. fixed length=00 in bits 6:5, bit len in bits 4:2
//{CC120X_RFEND_CFG1, 0x30}, // x30 gives return to rx after rxing
{CC120X_RFEND_CFG0, 0x0C}, //0x30 gives return to rx after txing
{CC120X_PKT_LEN, 0x08}, //pktlen, packet length 02 +4 bits for emids, 6-3/4 for pro
{CC120X_IF_MIX_CFG, 0x1C},
{CC120X_FREQOFF_CFG, 0x22}, //FOC_EN=x20, FOC_KI_Factor=02 was 20
{CC120X_MDMCFG2, 0x0C},
{CC120X_TOC_CFG, 0x40}, //TOC limit 2%
{CC120X_SETTLING_CFG, 0x08}, //Cal FS going from idle to rec or tx
{CC120X_FREQ2, 0x5A},
{CC120X_FREQ1, 0x00},
{CC120X_FREQ0, 0x00},
{CC120X_IF_ADC1, 0xEE},
{CC120X_IF_ADC0, 0x10},
{CC120X_FS_DIG1, 0x07},
{CC120X_FS_DIG0, 0xAF},
{CC120X_FS_CAL1, 0x40},
{CC120X_FS_CAL0, 0x0E},
{CC120X_FS_DIVTWO, 0x03},
{CC120X_FS_DSM0, 0x33},
{CC120X_FS_DVC0, 0x17},
{CC120X_FS_PFD, 0x00},
{CC120X_FS_PRE, 0x6E},
{CC120X_FS_REG_DIV_CML, 0x1C},
{CC120X_FS_SPARE, 0xAC},
{CC120X_FS_VCO0, 0xB5},
//{CC120X_FS_CFG, 0x0B}, //136-160Mhz
{CC120X_XOSC5, 0x0E},
{CC120X_XOSC1, 0x03},
};
Thanks,
John