• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 54 subscribers
  • Views 370 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

CC1310: Issues with send/recv at 5.0 kbps

CC1310: Issues with send/recv at 5.0 kbps -- Continued

VICTOR VALENCIA
Expert 1070 points
Part Number: CC1310

Hi TA12012

I was not able to respond to your original request since the issue was closed.  Here is your last suggestion

Agree with you that if it works at 2.5Kbps, it should work at 5.0kbps. 

The only difference between the two settings is the DSSS level, this is configured in the override section of the SmartRF.c file.


5kbps is defined as this:

// override_phy_long_range_dsss2.xml
// PHY: Configure DSSS SF=2
HW_REG_OVERRIDE(0x505C,0x0100),

2.5kbps is defined as this.

// override_phy_long_range_dsss4.xml
// PHY: Configure DSSS SF=4
HW_REG_OVERRIDE(0x505C,0x0303),

Can you take your one project that does work and just modify this one setting in both TX and RX and you should be able to modify from 5kbps to 2.5 and back again.

Regards,
/TA

I tried this and it did not make any difference.

Victor

  • 0
    TI__Mastermind 36395 points
    Victor,

    Did you validate the 32KHz clock is running?

    Thomas
  • 0 in reply to TA12012
    Expert 1070 points
    How do I do that?
  • 0 in reply to VICTOR VALENCIA
    TI__Mastermind 36395 points
    Victor,

    On page 986 of the user guide (www.ti.com/.../swcu117h.pdf) there is a section about how to route the 32KHz signal out to a pin on the CC device.

    The AON IOC contains the output enable control for the 32-kHz LF system clock output, and the clock
    signal has its own PORTID called AON_CLK32K (0x7). This makes it easy to output the clock signal to a
    pin. Map the clock to a chosen DIO, and enable the clock output by setting the
    AON_IOC:CLK32KCTL.OE_N to 0x0. The following two driverlib calls achieve the same result:
    #include <driverlib/aon_ioc.h>
    IOCPortConfigureSet(IOIDn, IOC_PORT_AON_CLK32K, IOC_STD_OUTPUT);
    AONIOC32kHzOutputEnable();
    This outputs the LF system clock signal in all power modes except for shutdown

    This signal can then be counted by a frequency counter, remember it has to be precisely 32768.0 Hz, we have a secondary RC oscillilator inside the CC device and this oscillator takes over if the external 32K fails, but the internal one is less accurate.

    So if you signal is exactly the 32768.0Hz then everything is good, it is less then the 32KHz XTAL has failed to start and you need to look at your layout and assemble.

    Regards,
    /TA
  • 0 in reply to TA12012
    Expert 1070 points
    OK. I will look into it and let you know.

    Thanks for your help.

    Victor