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Hi Team,
The FPGA as the slave and the CC3200 as the master device interact with the FPGA through SPI Master mode;
There are a few questions,
Best Regards,
Susan Ren
As a master the application is sending SPI transaction requests to trigger read and write.
There is no flow control, the slave should free the RX buffer in time (slower clock can be configured if needed).
Information on the available interrupts and the behavior in general can be found in the Technical Reference Manual (https://www.ti.com/lit/pdf/swru367).