CC3235SF: CC3235SF

Hi Venu,

You device is not communicate via UART using Uniflash. There may to be many reason for this fault.

• Do you use own hardware? If, so, was your hardware any functional? Was your hardware design reviewed by TI?
• How is done your UART connection? How do you control RST pin? What is your SOP mode?
• How many layer board do you use?

Jan

Thanks for your response.

Yes, the design is reviewed by TI, and it is 2-layer PCB.

Here, we are using this boot mode (UARTLOAD_FUNCTIONAL_4WJ)

Using the switch we are controlling the reset pin.

Coming to UART connection we used pin 55,57 those pulled up to 3.3V supply.

Here, I attached the SOP & UART configuration for your reference.

Regards,

Venu

As you said, we checked the voltage at particular points. We got the voltage 1.8V at 48th pin and 1.2V at 9th pin.

Even though we are unable to flash the code. here, I attached the error image that we got while flashing using JTAG.

Regards,

Venu

Hi Venu,

This error is expected because CCS is unable to communicate with your device. This will not move us forward.

It is good to know that you have VDD_DIGx and VDD_ANAx. But is hard to say if issue may to be related to two layer board or you have some other hardware fault (issue with XTAL, UART, internal DC-DC, reset issue, assembly issue, etc.). If I should guess, I will blame two layer board. From the past I remember only one e2e contributor which was able get to work CC32xx QFN at two layer. Other (maybe 20+) failed with this task. I am not sure if you have such luck.

• How looks power consumption from main rail during power on? Do you see there high peak current during radio calibration at startup?
• Do you see any activity at SOP2 pin and SPI pins for sFlash during startup?
• It is main XTAL working?

Jan

Hi Jan,

Okay, from your words, we understood that the issue is with 2 Layer PCB.

Sorry to say that we sent our entire design files to Ti for the verification. even at that time also, they didn't suggest us to design with 4 Layer.

Below are the observations,

• During power on, current consumption was 30mA to 100mA. 
• Activity at SOP2 means in our design it is pulled down to ground.
• crystal is also working.

Regards,

Venu

Hi Venu,

I am not able confirm to 100% that your issue is related to two layer board. But it is most likely.

I think you asked TI review of you schematic but not a full PCB layout. At CC3x35 layout guidelines is stated that four layer should be used.

• Static power consumption is not much useful. Please provide chart of dynamic power consumption after startup (like at chapter 2.4 of swra594a.pdf).
• No. By the activity I mean time behaviour after C3235 startup at SOP2 pin. You should see there "scanning" pulse at SOP2 line after startup.
• If main 40MHz XTAL is working this may to be good sign that internal DC-DC is working. How did you check that XTAL is working? Please make sure that you not affected XTAL by your measurement (e.g. like direct conductive connection of oscilloscope to XTAL).
• Did you see activity at SPI lines for sFlash? This can be check by logical analyser or multichannel oscilloscope.

If you will see activity at SPI lines for sFlash, it will mean that issue may to be something else (problem with UART like a swapped RX, TX lines; missing pull-up at RX line for SOP mode UARTLOAD_FUNCTIONAL_4WJ; issue with your SOP lines, etc.). Maybe you can try to use SOP mode 1-0-0 (2-1-0).

Jan

Hello Jan,

We will perform the test cases that you suggested us.

If it is not working even after performing all the test cases, we will go for 4 Layer design.

For that, can you please suggest the exact Blind & Buried vias diameter/Specification & track width to match 50ohm impedance for antenna.

Regards,

Venu Madhavi

Hi Venu,

Some recommendation regarding antenna path you can find layout guidelines. But you should still calculate antenna path using software (like Satrun PCB) and validate antenna path at real PCB using VNA. Be aware that even plastic device enclosure may to affect antenna performance. Here is nice video which demonstrate importance of optimisation at real hardware.

Jan

Hello Jan,

Thank you for your valuable suggestions and the support that you provided till now. But unfortunately, our board is not working as expected. So, we decided to work with 4Layer PCB and will send to TI for the verification. 

Requesting your support to verify the design files as we will send through connectivity-wifi-hw-reviews@list.ti.com mail.

Regards,

Venu Madhavi. M

Hi Venu,

Yes, I understood. Maybe there can be way how get to work CC3235 with two layer board, but re-design your board to four layer is a preferable way.

btw ... Do you want to use EAP (WPA2-Enterprise) WiFi security at CC3235?

Jan

Hi Jan,

Yes, We also need to use EAP (WPA3-Enterprise) WiFi security at CC3235SF.

Venu.

Hi Venu,

In this case you should re-consider to select other device. CC3235 supports for EAP security TLS 1.0 only. TI don't have plan to fix this issue. Almost all EAP networks at present time requires TLS 1.2. From this reason is not possible to use CC3235 at majority of EAP networks. I just want warn you about this limitation.

Jan

Hi Jan,

It's okay. No problem. As of now WPA2-Enterprise is enough for us. One more thing that we sent our 4 Layer design files to connectivity-wifi-hw-reviews@list.ti.com on 4/4/24. Still, we didn't get the response from them. Can you please help on this. 

Regards,

Venu

Hi Venu,

I am sorry, but I can't help you with this because I am not a TI employee.

Regards,

Jan

Hi Jan,

Okay.

It will be more helpful to us if you verify our design files. Can you please reply to madhavi.m@altiux.com if you are able to verify?

Thanks in advance.

Regards,

Venu

Hi Venu,

Sorry I am not able review your design. Please wait for answer from TI side.

Jan

okay Jan, thank you so much for your support till now.

Venu

Hi,

Just noticed you would like to get a schematic/layout review for a 4 layer design.

It will be reassigned to an HW expert for further support.

Shlomi

Thank you shlomi 

Thank you, Jonathan.

Hi Jan,

In CC3235SF, 48th pin description is:

But as per reference schematics, the connection is established externally as shown.

Can you please confirm whether it is already connected internally, or we have to connect it externally.

Regards,

Venu

Hi Jan,

Which PCB material will be more preferable for designing with CC3235SF12RGKR?

Regards,

Venu

Hi Venu,

I think standard material like FR4 should be fine. But RF output path need to have impedance matching (impedance calculated and validated at real PCBs). For more details see swru536 chapter 2.

Jan