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CC3551E: Clarification on SoP Modes for CC3551E & CC3501E

Part Number: CC3551E
Other Parts Discussed in Thread: LP-EM-CC35X1,

Tool/software:

Hi Team,

I am working on a board based on the LP-EM-CC35X1_RevE3_DesignFiles and have CC3551E on it.

Could you provide details on the SoP modes defined by the LOGGER and P52_GPIO37 pins? These are not mentioned in either the datasheet or the TRM.

Thanks in advance for your help.

Best regards,
Robert

  • Hi Peter,

    These 2 pins are SOP pins and are being used for TI's internal development purposes.
    They are designed (internally) so that the Logger will stay at high logic level, and P52_GPIO37 will stay at low logic level during power-up.
    So you don't need to have these pulls connected to them (externally) in your design, or else you might cause an interference to this mechanism. 

    However, we do recommend having the Logger pin connected to a header pin, so you can use whenever you'll need to capture FW logs.

    Best regards,
    Omri

  • Hi Omri,

    Thanks for reply. 

    Does this mean GPIO37 is reserved and I cannot use it for other purpose?

    Cheers,
    Robert

  • Hi Robert,

    GPIO37 can be used for general purposes (as the other GPIOs) but keep in mind that since it's a SOP pin it's important to not have it connected to a trace that will pull it up during power-up. That's because, as I said earlier, this pin should stay at low logic level during power-up.

    Best regards,
    Omri