• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 22 subscribers
  • Views 674 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CDCE62005 clock generator problem

Bhupesh Patil
Intellectual 440 points
Other Parts Discussed in Thread: CDCE62005

I am using CDCE62005 interfaced with ALTERA STRATRIX FPGA. The primary and secondary reference clocks are LVDS and external termination is provided for both.

My worry is,  it is written in the datasheet that on powerup device is configured via EEPROM which is factory programmed.  Due to that Primary and Secondary are set to LVPECL AC termination. will it  damage the input clock buffer? I don't have an idea.

Please reply early if anybody knows. I have some academic deadlines to finish the project.

 

 

 

  • 0
    Prodigy 105 points

    Hi!

    I don't think if it can do anything to damage those input buffers. The worst thing is a little more dissipation and sh*tty clock. But if you feel that's unsafe, assert the SYNC pin (disable outputs) while configuring the chip to proper output settings.

    Regards,
    Bagoj

  • 0 in reply to Bagoj
    Intellectual 440 points

    Thanks Bagoj for the reply. After investing so many days to understand the register settings, I  made it work finally.

  • 0 in reply to Bhupesh Patil
    Prodigy 10 points

    Hi,

       I am having trouble reading the default registers on power-up through SPI interface. I can read some registers fine but some of them seem to be corrupted.

    Is there some special power sequencing required for this chip ? What could be other causes for EEPROM to RAM loading failure  or RAM corruption?

  • 0 in reply to Kiran V
    Genius 4530 points

    Hi Kiran,

    Yes, CDCE62005 does have a power-up sequence.

    It has been explained in the form of a device operation FSM in the datasheet. On power-up, it enters into auto-calibration mode, after which EEPROm contents are loaded into RAM.

    Ensure that you are following this sequence.

    Corrupted registers could be a result of a faulty code or faulty values to Reserved registers.

    Hope this helps.

    Regards,

    Sid

  • 0 in reply to Sid
    Intellectual 440 points

    Hey Kiran,

    As Sid suggested about FSM given in a datasheet...go through that.... But please go though all register settings carefully and make sure u r doing all the things correctly according to your hardware.

    I did a simple thing to get confidence for the circuit functionality

    1. The right termination settings for source clock

    2. disabled all the used output clock buffers.

    3. Just diverted input clock to the unused clock output pins using proper output buffer and mux seetting. do not use pll output or else

    Do this simple steps and see whether u r getting the output.....for my hardware input clock is LVDS and output clock LVCMOS.

  • 0 in reply to Bhupesh Patil
    TI__Expert 4150 points

    The conclusions drawn earlier in this forum are correct. the input buffer when configured to PECL will not be damaged by driving an LVDS signal into it.

    Please also note that you can also re-program the EEPROM, so the device starts up with the proper settings after power up.

    Best regards, Fritz