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JFET + transimpedance amplifier

Other Parts Discussed in Thread: OPA847, OPA695, OPA657

I'm currently trying to design a very low noise transimpedance amplifier.

Here are the requests :

Bandwidth : 28 MHz

Transimp : 40 kOhms

Source capacitance : 30 pF

Noise : as low as possible

I first considered OPA847 but it's still too slow and I'm stuck with a strong current noise

Desiging a 2-stage amplifier could work but, again,  the noise gets too high

I am now considering OPA847 + fast JFET (BF862) input stage as a common source

do you have some experience with such a design ?

cheers

Julien 

  • Julien,

    A bit more information would be helpful here.  What is the amplitude range of the input signal?  When you say "the noise gets too high", what is your specification for "too high"?  Thanks --

  • my  dynamics is pretty high : from 0.1 uA to 25 uA. at the 0.1 uA level, I woule like to reach an accuracy of 5%.

    I would need a noise of about 100 uV RMS to get that kind of accuracy. I think that it's not something I can reach with a standard transimpedance design.

    cheers

    Julien

  • Julien,

    The OPA847 is going to be your best option here and will provide nearly the best noise performance available in an integrated amplifier.  It is highly decompensated, and already achieves 0.85nV/rtHz voltage noise, so adding an additional JFET on the input would likely increase, not decrease the noise.  To reach the gain and bandwidth you require, you will need multiple stages, such as an OPA847 + OPA695, allocating as much gain to the OPA847 as possible without compromising your bandwidth requirement to minimize noise.  I have attached a TINA file demonstrating such a configuration.

    0511.OPA847 + OPA695.TSC

  • Dear Bart,

    thanks for your detailed answer. However, I'm not completely convinced by your arguments.

    As far as the voltage noise is concerned, you're certainly right. But the current noise of OPA847 is high. 

    Coupling  a large transconductance JFET together with the OPA847 should permit to overcome that limitation.

    Moreover, a small gain (a JFET in common source configuration) should lead to a higher bandwidth for the same transimpedance.

    I hope to avoid the 2nd stage OpAmp that way.

  • In a low frequency application, I agree that a FET input stage would be preferable in terms of noise.  But at higher frequencies, the voltage noise term becomes dominant, and an amplifier with lower voltage noise will produce lower overall noise.  As an example, consider the OPA657 (decompensated, JFET input) against the OPA847.  Per the design equations here, I have shown the input referred current noise across various noise integration limits (Cs and Rf held constant).

    Though I am not an expert in the latest and greatest discrete JFETs available, I would anticipate that this trend would hold in the topology you are describing.  If you implement such a solution, I would be interested in the results.

  • What value of transimpedance (Rf) did you put in the dimulation ?

    There are only few adequate discrete JFET. Among them are the 2SK170 and, even more adequate, the BF862.

    However, I have strong difficulties to produce the proper .LIB file for those parts...

  • In the example I used Cs=30pF, Rf=10kohm.  Rf can also affect which type of amplifier will have lower overall noise in a given application.

    Your post regarding the JFET model was moved to the modelling forum, so hopefully that will be addressed, and simulations can provide additional clarification here.

  • agreed . The higher Rf, the better the FET input OpAmp. 

    I hope that I'll be able to progress with the design of the 2-stage TIA very soon. It mainly depends on the availibility of the libraries.

    Cheers and thanks for you help.

    Julien