Hello,
Please answer following question from customer.
Datasheet doesn’t explain when following flag are cleared.
Please explain the clear condition for each flag.
Best Regards.
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Hello,
Please answer following question from customer.
Datasheet doesn’t explain when following flag are cleared.
Please explain the clear condition for each flag.
Best Regards.
Hello Mahmoud-san,
Thank you for your answer.
I understand that D[5]: TOKEN_ERR will be cleared if the following answer is correct.
I need same kind of information when following flag is cleared. (After SPI read or ……..)
SEQ_ERR
TIME_OUT
TOKEN_ERLY、
Best Regards.
[Answer] These bits are updated at the end of each WD cycle interval.
These bits are cleared/initialized by power-on reset event and when NRES is driven low, and updated (not cleared) at the end of each WD cycle interval.
Hello,
Please answer additional following question.
I tested the behavior of TIME_OUT flag using TPS65381EVM.
It was not return to “0” at the end of good WD cycle, and returned to “0” only when TIME_OUT flag is read by SPI. Ant EVM behavior is different from answer posted on Aug 02 2014.
So please reconfirm the behavior of TOKEN_ERR, SEQ_ERR and TOKEN_ERLY flag if these return to “0” at the end of good WD cycle and/or after SPI read, and write down the correct behavior in attached file.
Best Regards.