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afe7225: power meter problem

Oguzhan Orhan
Prodigy 60 points
Part Number: AFE7225

Hi,

We are using the power meter feature of AFE7225 for monitoring the received power level in dBfs. We want to develop an algorithm which sets the RF gain before ADC with respect to the value read from AFE7225's power meter. If there is no signal, it shows "0" meaning that the signal level at ADC is <-15dBfs.  For increasing the power that comes to ADC, we will decrease the attenuation level until the AFE7225 reads the power level -1dBfs (value = 15). However, when we increase the input power more after getting -1dBfs, we saw that there is a 10dB margin in -1dBfs level and later if we increase the power more, it turns to "0" value due to high level of the power.

If the read power from AFE is "0", we don't know why it is zero. It can stem from low level of signal level or huge level of signal level. If it is due to huge level signal level and if our algorithm says to increase the gain of the circuit by thinking there is a low level signal, maybe the device will be damaged due to high power level of the signal. Is there any way for solving this problem?

Regards,

  • 0
    TI__Intellectual 2750 points
    Hello Oguzhan,
    I have sent your question to an engineer familiar with this device.
    Regards,
    Brian
  • 0
    TI__Mastermind 18095 points
    I understand the issue. There are two areas of concern. You mentioned there is 10 dB of margin after the power meter shows 15 = -1 dBFS. This does not seem proper. When the device first reads 15 = -1 dBFS what is the actual captured pattern? Is it actually -1dBFS or something 10 dB lower. This may be an issue of the peak power (of modulated signal) reaching -1 dBFS while the average power is say 10 dB lower. I recommend to increase the integration interval to effectively increase the averaging. This should make the output detection more stable.

    I suspect that when the input signal gets too high the over-range bit is set and the output samples (and power detector) are unreliable. I recommend to monitor the over-range bit in addition to the power meter results so that if an over-range is detected, the attenuator can be programmed to a significant attenuation regardless of the power meter state.

    --RJH
  • 0 in reply to RJ Hopper
    Prodigy 60 points
    We are using our own waveform that is generated from AFE7225 DAC. We convert the signal into RF frequency via an RF front end. We are doing loopback tests by connecting TX to RX with safe attenuation. We can set output level of the TX with a variable attenuator from RF front end. We also have an RF front end with programmable gain in RX. Initially, we are generating low level of output power from TX and increasing the output level slowly. We see 1dB increase in read power in dBfs when we increase the tx power 1dB. After we read value of 15 (-1dBfs), we continue to increase the tx power in 1dB steps to be able to test over range situation. After increasing 10dB more, it turns to 0; therefore, we interpreted this situation that there is a margin. Probably data is corrupted in this situation; we did not test it yet. We will define top limit according to our tests.

    We checked over range bit but we have a problem here. We set 1 "OVR_EN_RX" pin in address 0x337 and read the D0 bit in the same address for getting over range information. When we give high level of power (which makes power meter value from "15" to "0") to RX, this register does not turn to 1. Is there any other setting to activate the over range indicator?

    Thanks,
  • 0 in reply to Oguzhan Orhan
    TI__Mastermind 18095 points
    In addition to setting the "OVR_EN_RX" pin in address 0x337, you need to enable the master override bit. Per the datasheet: All the modes of register 0x337 work only if MASTER_OVERRIDE_RX (Bit <7> in Address 0x33A) is enabled.

    Have you actually captured the signal using HSDC Pro or equivalent to view the FFT of the captured waveform? I am curious what the spectrum looks like as you transition to the "10 dB of margin" space and "overrange" space. The 10 dB of margin space does not seem right unless you are dealing with a high peak-to-average (PAR) signal. Then that may make sense, though increasing the power meter averaging should mitigate. If you are truly overdriving the ADC input the SNR performance from the FFT plot will degrade very quickly.
  • 0 in reply to RJ Hopper
    Prodigy 60 points

    Actually, we enabled the master override bit for 2-wire LVDS mode. Although it is active, we could not get over range warning. What could be the problem?

    You are right, there is no 10dB margin. We supposed there can be 10dB margin, because we read the same level from power meter when the power increases 10dB more. But our data corrupted in over range. We need to get over range warning but we could not get yet.

  • 0 in reply to Oguzhan Orhan
    TI__Mastermind 18095 points

    Acknowledged.  Let me investigate Over-range in a bit more detail.  --RJH

  • 0 in reply to Oguzhan Orhan
    TI__Expert 4880 points

    Hey Oguzhan, 

    Please send me the register configuration settings and let me know what order the bits are arranged. (LSB->MSB or MSB<-LSB). Also can you send me maybe an overview of how your code is processing the data from the AFE, line by line? Are you using an FPGA for processing? Also as a quick check, make sure your data orientation register setting (MSB first or LSB first: reference reg x33A pg 51 AFE722x data sheet) in the AFE is aligned with how your processor is expecting to receive information. 

    Yusuf

  • 0 in reply to Yusuf%20Agoro
    Prodigy 10 points

    Hi Yusuf,

    We are using FPGA for processing. Our data orientation register set to LSB first (it is expected). When I tried to MSB first, I didn't observe any changes on coarse power meter and also  overrange indicator bit. I don't understand how LSB or MSB affect power meter?

    Register Configuration:

    0x3AA -> 0x82 (in our setting)

    0x3AA -> 0x8A (I change it for trying MSB first)

    Mustafa

  • 0 in reply to Mustafa Tosun
    Prodigy 60 points

    Hello,

    We are still waiting a response, we could not solve the problem, yet. Can you help us, please? Do you have firmware of AFE7225 GUI software for ZC706 evaluation board?

    Thanks,

  • 0 in reply to Oguzhan Orhan
    TI__Expert 4880 points

    Hey Oguzhan, 

    My apologies for the wait. Unfortunately, I am still currently debugging this. Give me until the end of the week and i will have an update for you. 

    Thank you for your patience.

    Yusuf

  • 0 in reply to Yusuf%20Agoro
    TI__Expert 4880 points

    Hey Oguzhan, 

    This issue has been forwarded to an apps engineer who has prior experience with this device. He should be in contact with you before the week is over. 

    Yusuf

  • 0 in reply to Yusuf%20Agoro
    Prodigy 60 points
    Hey Yusuf,

    Thanks fo your interest. We are still waiting a response but we have also another issue. What is the input power dynamic range for ADC of AFE7225 and optimum input power, in dBm?

    Regards,