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DRV8805 Digital signal timing condition

masahiko shimizu
Guru 11235 points
Other Parts Discussed in Thread: DRV8805

Hi

My customer is using DRV8805.
He is worrying about noise on digital line.

This is the noise at EMC test.
Noise by EMC test is operated DRV8805 without intending.
For this noise, We will use RC filter on digital pin.

1. About step line
Could you tell me the max value of step high pulse width for not ensuring step high?
-> I saw twh(Min 1.9us) in datasheet page of 6.
Is the value of less than 1.9us?
Maybe, I think there is a possibility that it'll be High input of a clock even below the value of this(1.9us).
If it cannot define, Please advice me?

2. About nEnable line
Could you tell me the max value of low pulse width for not ensuring Enable?
If it cannot define, Please advice me?

Best regards
Shimizu

  • 0
    TI__Mastermind 26065 points
    Hi Shimizu,

    I think we only define the MIN time of the duration of the logic HIGH or LOW for valid inputs. But we don't define what is the MAX duration to keep inputs invalid. Anything <2us will still have the change to make the inputs valid. So if we apply filter, we should creat a time constant to make sure at the 2us point, the voltage is < VIL for logic HIGH and > VIH for logic LOW to make sure there is no false action by noise.

    Best regards,
  • 0 in reply to Wilson Zuo
    Guru 11235 points
    Hi

    Thank you for your advice.

    Thanks
    Shimizu