DRV8308: Pre-Driver PWM Pulse Width with Closed-Loop Speed Control

Hi Jim,

My apologies for the delay.

"What is the balance between PWM frequency, duty cycle and the control loop for closed-loop control with Clock Frequency Mode?

I have an application that normally needs a motor RMS current of 5 to 20 mA and has a maximum current limit of 340 mA (calculated from the maximum torque limit). The motor has low winding inductance (85 uH) and resistance (5.5-ohm). I plan to operate the DRV8308 with a supply voltage of 8.5 V. Due to the low winding inductance, the di/dt is very fast, so I would like to understand the relationship between using a high PWM frequency and the ability to manage speed and current."

The duty cycle is used to reach the desired speed. The faster frequencies are used to minimize the torque ripple. At low inductances, the PWM frequency is typically increased.

The higher PWM frequency creates more switching losses; from turning the FETs on and off and when the body diodes are conducting during the dead time.

"Also, if the PWM Ton time (PWM pulse width) is shorter than the Current Limit blank time (TBLANK), does the Current Limit circuitry even have an impact? (I presume the blank time is reset at the beginning of every PWM cycle.)"

You are correct. The current limit circuitry does not activate until the blank time expires.

"As for the PWM output for the MOSFET pre-drivers (assuming 120° commutation, not sine-wave-drive), my understanding is that the duty cycle is based on the output of the speed control loop (differentiator, integrator, digital filter, etc.) which results in a 12-bit duty cycle to be applied as Ton for the next PWM cycle. That said, if the PWM frequency is set to 200 kHz, the PWM cycle time is 1/200 kHz = 5 us. Then with the 12-bit duty cycle, the PWM Ton time can be as small as 5 us / 4095 = 1.22 ns (e.g. a 50% duty cycle would have a 2.5 us Ton time or a count of 2048 where 2048*1.22 = 2.5 us). Is this the correct understanding of how the PWM output works?"

"However, a minimum PWM Ton time (PWM pulse width) of 1.22 ns doesn't even seem realistic since it would require a transistor gate charge of about 0.15 nC just to turn on with the DRV8308 maximum output drive current of 130 mA (rise time = gate charge [C] / pre-driver current [A]). That doesn't even allow the FET to fully conduct and a power MOSFET with that low of a gate charge is not readily available to the masses."

Yes, your understanding is correct to a point. The 100MHz clock limits the minimum pulse width to 10ns. Even it the minimum duty cycle is set to 10ns, this is not realistic. The intention is to allow maximum flexibility at all PWM frequencies.

A clarification is that the SPEED register is scaled depending on the PWM frequency.

For 25kHz,   bits 11:0 are used to set the duty cycle, resulting in 1/4095 duty cycle settings.
For 50kHz,   bits 11:1 are used, resulting in 1/2047 duty cycle settings
For 100kHz, bits 11:2 are used, resulting in 1/1023 duty cycle settings
For 200kHz, bits 11:3 are used, resulting in 1/511 duty cycle settings

Again, some of these settings may not be realistic.

"Overall, I'd like to make sure I am correctly understanding the closed-loop speed control operation and the associated PWM output duty cycle operation and timing resolution. Once I correctly understand those and the relationship between PWM Ton time and Current Limit blank time, I believe I can determine how to properly use the DRV8308 in my application."

Please let us know if you have more questions.