Hi,
I have a question about AM5728 DDR3L layout routing.
In AM572x datasheet, there are DDR3L layout guideline and I'm reading it.
Also I'm refering to AM572x IDK schematcis, and there was difference between
guide and schematics.
In IDK schematics, Address Line are connected to VTT via termination resistor and
also connected to VDD_DDR and GND via capacitor. Please see the attached IDK schematics.
But in guidline, its only connected to VTT via termination registor.
Why Address Line are connected to VDD_DDR and GND via capacitor?
Which layout should I use in customer board?
best regards,
g.f.