TAS5756M: Question about GVDD_REG power supply

Satoshi

Guru 19575 points

Part Number: TAS5756M

GVDD_REG power supply specification is not described in datasheet.

Waveform for startup sequence is attached below;

・On startup to 10 sec: 5.4V output and the after is 6.8V output.

・After I2C communication(Reset), GVDD is dropped to 5.4V for 1 sec and after become 6.8V.

Please let me know about two points question below;

①Is above waveform correct operation?

②Please let me know timing for read Vspk_GAIN/FREQ's DC voltage.

Best regards,

Satoshi

over 5 years ago

0 Shawn Zheng over 5 years ago

TI__Mastermind 24835 points

Hi Satoshi-san,
We are looking into this and will get back you soon later.
Best regards,
Shawn Zheng

0 Satoshi over 5 years ago in reply to Shawn Zheng

Guru 19575 points

Shawn Zheng-san

Thank you for reply,
I understood your status, I looking forward any update later.

Best regards,
Satoshi

0 Andy Liu (BMS) over 5 years ago

TI__Guru 52115 points

Hi Satoshi,

What are the i2c commands you sent in your measurement?

Andy

0 Satoshi over 5 years ago in reply to Andy Liu (BMS)

Guru 19575 points

Andy-san

I attached I2C command data, please see below.

I2C_command.xlsx

Best regards,

Satoshi

0 Satoshi over 5 years ago in reply to Satoshi

Guru 19575 points

If there lack information, please let me know.
I will confirm to customer.

0 Andy Liu (BMS) over 5 years ago in reply to Satoshi

TI__Guru 52115 points

Hi Satoshi,

Let me explain why you would see the transition from 5.4V to 6.8V (See what is highlighted below).

After the TAS5756M is powered on, the GVDD_REG voltage will be around 5.4V if NO I2S clocks are provided. In addition, its voltage will be close to 7V when the TAS5756M is fed with I2S clocks and data.

The transition from 5.4V to 6.8V in your scope capture is because the I2S clocks in the customer systems are starting to run at that time.

0 Andy Liu (BMS) over 5 years ago in reply to Satoshi

TI__Guru 52115 points

The second transition from 6.8V to 5.4V is due to the following i2c command. Basically, the GVDD_REG voltage drops down to around 5.4V when it goes to the standby mode.

Andy

0 Satoshi over 5 years ago in reply to Andy Liu (BMS)

Guru 19575 points

Andy-san

Thank you for advice, I understood very much.
I looking forward answer about ②.

Best regards,
Satoshi

0 Andy Liu (BMS) over 5 years ago in reply to Satoshi

TI__Guru 52115 points

As far as I know, the gain and switching frequency settings are latched during power-up and cannot be changed while the device is powered.

Andy

0 Satoshi over 5 years ago in reply to Andy Liu (BMS)

Guru 19575 points

Andy-san

Sorry for additional question about ②,

When power-up timing, which is correct for 5.4V or 6.8V?
If 5.4V is correct, TAS5756M can't set 26dB / 8 x fSYNC by datasheet Table 15.
Is there any measure?

Best regards,
Satoshi

0 Andy Liu (BMS) over 5 years ago in reply to Satoshi

TI__Guru 52115 points

Hi Satoshi,

When the voltage on the SPK_GAIN/FREQ pin is latched, the GVDD voltage is around 7V.

Andy

0 Satoshi over 5 years ago in reply to Andy Liu (BMS)

Guru 19575 points

Andy-san

Thank you for reply,

About Table 15; When 26dBv and 8 × fsync, is GVDD voltage around 5.44V~6.6V?
Addition, please let me know about response time for detect and latch the voltage.

Best regards,
Satoshi

0 Satoshi over 5 years ago in reply to Satoshi

Guru 19575 points

Any update on this?

0 Andy Liu (BMS) over 5 years ago in reply to Satoshi

TI__Guru 52115 points

Hi Satoshi,

No. The voltage presented on the SPK_GAIN/FREQ pin is digitized and then decoded into a 3-bit word which is interpreted inside the TAS5756M device to correspond to a given gain and switching frequency.
The 5.44V to 6.6V voltage range is the one corresponding to 26dBV and 8 × fsync.

Andy

0 Satoshi over 5 years ago in reply to Andy Liu (BMS)

Guru 19575 points

Andy-san

Sorry for my reply delay,

Customer had additional question,

How long is the timing delay for start up (power on) to read Vspk_GAIN/FREQ's DC voltage?

About after start up, customer case is at first GVDD: 5.4V on 10 second and after become 6.8V. (It is not continuous 6.8V)

They want to confirm read timing is really 6.8V or not (5.4V).

Best regards,

Satoshi

0 Andy Liu (BMS) over 5 years ago in reply to Satoshi

TI__Guru 52115 points

Hi Satoshi,

As I mentioned before, the transition from 5.4V to 6.8V in your scope capture is because the I2S clocks in the customer systems are starting to run at that time. The gain and switching frequency settings latching will only happen after this transition, which means GVDD is 6.8V when latching occurs.

Andy

0 nazim zmirli26 over 5 years ago in reply to Satoshi

Prodigy 20 points

The constant power yield of any speaker is controlled by the warm execution of the enhancer just as constraints set on it by the framework around it, for example, the PCB arrangement and the encompassing working temperature.

0 Satoshi over 5 years ago in reply to nazim zmirli26

Guru 19575 points

Thank you for reply,

Sorry for additional question for timing diagram attached before;

①About Andy-san answered "run at that time", what is concrete signal?
　Is CLK/DATA input one-ckock correct?
②Is there timing specification and timing chart?
　Customer hope to confirm timing spec for GVDD start up, change to 5.4V~6.8V.
③About first GVDD change: 5.4V to 6.8V,
　What is trigger of change?
　Is trigger depend on time delay and this time is about 10 sec, correct?
④About second GVDD change: 6.8V to 5.4V to 6.8V,
　This recovery time: 1 sec is large differ from first change: 10 sec, why second GVDD change became fast?

Best regards,
Satoshi

0 Andy Liu (BMS) over 5 years ago in reply to Satoshi

TI__Guru 52115 points

Hi Satoshi,

Can you post your new questions into a new thread? Thanks.

Andy

0 Satoshi over 5 years ago in reply to Andy Liu (BMS)

Guru 19575 points

Andy-san

I understood,
I will make new thread near last question and modify customer information.

Best regards,
Satoshi

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TAS5756M: Question about GVDD_REG power supply