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PCM1802: Power up sequence

Part Number: PCM1802

Hi all

Would you mind if we ask PCM1802?
Please refer to the attachment file.
20181218_PCM1802.pdf

※ On the file, "Input mute" means Low is no input, High is to start inputting. 

Our customer uses this sequence.
If there is some problem, could you let us know?

Using this sequence, there is 30mV offset on ADC converted data.
->We assume that if there is no power up sequence, we inform the customer that there is another problem.

Kind regards,

Hirotaka Matsumoto

  • Hi team

    If you have some update for our question, could you share us it?
    And then, in addition to our last update, we would like to confirm one point.

    After PDWN is toggled(release power down mode), should we wait for the term 1024 system clocks and 4480/fs?
    In other words, should we regard PDWN toggling operation as "Internal Reset" on the datasheet P14?

    And then, there is some incorrect value of LRCK, BCK and SCKI.
    We changed the correct value on 18th December.

    Kind regards,

    Hirotaka Matsumoto

  • Hi Matsumoto-san,

    I will look into this and will have feedback. Thanks.

    Best regards,
    Ravi

  • Ravi san

    Thank you for your cooperation.
    The customer needs this reply by this Friday.
    We are looking forward to your update.

    Kind regards,

    Hirotaka Matsumoto

  • Hi Matsumoto-san,
    in the first thread, the comment regarding the input mute is bit confusing as PCM1802 does not have MUTE input. Can you please elaborate?

    Regarding PWDN input, this input would usually supercede the internal reset and the part should have normal output once we pull the PWDN high, followed by the 4480/fs cycles.

    Finally, can you please send me waveforms regarding the offset you mentioned for the output? I am not sure what may be causing this issue at the moment and need more info...Is this observed on their board or EVM?

    Thanks.

    Best regards,
    Ravi