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TLV320DAC3203: Master Clock Input

Tivinc
Prodigy 75 points
Part Number: TLV320DAC3203

Happy Tuesday,,

I haven't experimented with a Demoboard or chip yet, but I was wondering if the Master Clock Signal is required when using I2S/TDM with the TLV320DAC3203? 

Look forward to the feedback. 

  • 0
    TI__Guru* 84915 points

    Hi, Tivinc,

    When the TLV320DAC3203 is configured in slave mode (WCLK / BCLK provided by an external processor/device), the master clock is not required. The sampling rate and rest of internal clocks can be generated by the BCLK.

    In master mode (WCLK / BCLK generated by the TLV320DAC3203), MCLK is required.

    For additional details about the I2S configurations, please take a look at the document below:

    http://www.ti.com/lit/an/slaa469/slaa469.pdf

    Please let me know if you have additional questions or comments.

    Best regards,
    Luis Fernando Rodríguez S.