Hi Daniel,
1.-There is no requirement on the power up sequence. But the device will behave slightly different depending on what supply comes up first.
Generally the device has a power up control that is connected to the 1.8V supply. This will keep the whole device disabled until the 1.8V supply reached a sufficient voltage level. Then it switches on all internal components. This also includes the outputs. So if you have 3.3V Vddout available before the 1.8V, the outputs stay disabled until 1.8V supply has reached a certain level.
In your case, 1.8V present before 3.3V, the outputs get switched on already and will swing with whatever level is present on Vddout.
The bottom line is that there is no problem with the power up sequence for the CDCE925, it depends on the application.
2,3.- jitter depends on the setup (rms jitter, phase noise, cycle to cycle and peak to peak jitter), even if an output is bypassing the PLL, it might possibly degrade the input jitter if there are other PLLs active, please take a look at the plots below that illustrate this:
2.1. Y1 phase noise when Y1 is bypassing the PLL, but PLL is active.
2.2-Rms jitter when all PLLs are bypassed, acting as a buffer
3.-Rms jitter when PLL is active
