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DAC38RF83: Sync devices when the main clock is from DACCLKSE

Moti Cohen
Prodigy 170 points
Part Number: DAC38RF83

Hi

I need to sync 3 devices. 

Main device input clock at DACCLKSE = 6000MHz.

Secondary input clock at DACCLKDIFF = 250MHz

SYSCLK = 250MHz  syncronized in phase to DACCLKDIFF. 

Is it possible to sync all devices using when the main clock is from DACCLKSE (6000MHz)?

  • 0
    TI__Genius 9695 points
    Hi Moti,

    Yes, it is possible to SYNC multiple devices with the DACCLKSE as the main clock. But note that the device performance was characterized using the differential clock input so performance with DACCLKSE may be different.

    Thanks,
    Eben.
  • 0 in reply to Ebenezer Dwobeng
    Prodigy 170 points

    Hi Eben

    Do you have any block diagram that explain the connections to FPGA (when the main clock is DACCLKSE)?
    Do I need to use all the 3 inputs DACCLK SE + DACCLK Diff + SYSREF?
    DACCLKSE = 6000MHz
    DACCLK Diff = 250MHz
    SYSREF in sync to DACCLK Diff

    During synchronization process, do I need that the SYSREF rising edge will be in sync to the DACCLKSE?

    Thanks

  • 0 in reply to Moti Cohen
    TI__Genius 9695 points

    Hi Moti,

    - Using DACCLKSE will not change the connections to FPGA. DACCLKSE and DACCLKDIFF are connected to a 2:1 mux that selects one of these 2 inputs. See figure 52 in the datasheet.

    - You dont need all 3 inputs, you only need one clock input and SYSREF

    -You only need to make sure that there is a fixed timing relationship between SYSREF and the DACCLK always.

    If you will be using the 6GHz external clock as the DACCLK, then I will suggest you look at the SYSREF capture circuit in datasheet section 8.3.10. This will help you to reliably capture sysref for synchronization.

    Thanks,

    Eben.

  • 0 in reply to Ebenezer Dwobeng
    Prodigy 170 points

    Hi Eben

    Thank you for your clarifications.
    As I understand, when I use the SYSREF at the same time with DACCLK all DACs will be in sync.

    But how do I sync the FPGA JESD204B (class 1) Tx section link, to all DACs if the FPGA reference clock is
    only a division of the 6000MHz DACCLK (250MHz)?
    Is it necessary that the JESD204B transmitter (FPGA) and all JESD204B receivers (DAC) will receive the SYSREF simultaneously at the same time?

    Regards

    Moti

  • 0 in reply to Moti Cohen
    TI__Genius 9695 points
    Hi Moti,

    SYSREF should be distributed in a deterministic way to all FPGAs and DACs to achieve synchronization. This means that you can distribute SYSREF to all DACs and FPGAs simultaneously or make sure that if there is any delay in SYSREF distribution, this delay is always the same.

    Thanks,
    Eben.
  • 0 in reply to Ebenezer Dwobeng
    Prodigy 170 points
    Hi Eben

    Maybe I do not understand the JESD204B process.
    Assuming there is 4 JESD204B Tx from FPGA that connected to 4 DACs.
    To sync all 4 DACs to be at the same phase I know that it is imported that all 4 DACCLK and SYSREF to DACs will be at the same time.

    Question about the SYSREF to FPGA:
    For DACs synchronization, do I need to active SYSREF at FPGA?
    If so, does the DACCLK and SYSREF to FPGA must be exactly at the same time as the DACCLK and SYSREF that feed the DACs?

    Thank you for your explanation
    Moti Cohen
  • 0 in reply to Moti Cohen
    TI__Genius 9695 points
    Hi Moti,

    There are knobs such as RBD (release buffer delay) and DAC output delay register that can be used to align the phase of all TX outputs provided there is a fixed delay between the outputs. If you can ensure SYSREF is sampled at the same time at all TX, then that is ok too since you can configure all the JESD and delay parameters in DAC the same.

    Yes, you need to distribute SYSREF to FPGA.
    The requirement is that SYSREF sampling at the FPGA by the device clock is deterministic but if you can ensure that SYSREF is sampled at the same time at the FPGA and all DACs, that is ok too.

    You may also use an AND gate to combine the SYNC~ from all DAC devices into one SYNC~ signal for the FPGA

    Thanks,
    Eben.
  • 0 in reply to Ebenezer Dwobeng
    Prodigy 170 points
    Hi Eben

    Thank you again for your explanation.
    I read about the RBD register and maybe I can use it.

    I think you answer my question but to be sure I will ask it again (Please).
    I have two groups.
    Group A with 4 DACCLK and 4 SYSREF. Group A is connected to 4 DAC devices. SYSREF A is in phase as DACCLK A.
    Group B with 1 DACCLK and 1 SYSREF. Group B is connected to FPGA device. SYSREF B is in phase as DACCLK B.
    DACCLK A and DACCLK B are at the same frequency but nut at the same phase.

    My question:
    Should the phase time of SYSREF at group A must be in the same phase timing as SYSREF at group B?

    Regards
    Moti Cohen
  • 0 in reply to Moti Cohen
    TI__Genius 9695 points
    Hi Moti,

    The requirement for synchronization is to keep the phase of SYSREF in group A relative to SYSREF in group B constant.
    Also phase of DACCLKA relative to the phase of DACCLKB must be constant. This will ensure that the latency is always the same after every power cycle.

    Thanks,
    Eben.