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ADS1282: Data rate when operating in modulator output mode

Dean Gacita
Intellectual 300 points
Part Number: ADS1282

TI;

I am working with the ADS1282 and have a couple of questions on data rate (phase through the chip). I am looking for the fastest data rate (lowest phase) I can get. My question surrounds Table 5 on page 18. If I select 00 and use Bypass modulator mode what will I get as a data rate the lowest group delay?

Again looking at page 18 Table 6 of the datasheet I see if I select DR at 100 I get a data rate of 128K = 7us phase delay. Bypassing the programmable digital filter - is it correct for me to assume that would be my total group delay?

What I am after in the long run is to offer my customers of the system I am developing is to either use the rawest of data I can provide with the minimum delay or to consume more of the control system delay by off loading the digital filtering onto the ADS1282.

Thanks

Dean Gacita

  • 0
    TI__Mastermind 44610 points

    Hi Dean,

    Referring to to Figure 37 on the same page, the modulator output mode bypasses all of the internal digital filtering of the ADS1282. Instead of getting a single settled conversion result, you will get a digital bit-stream and will have to compute the value given by equation 5. From there it would be up to you to implement a digital filter in your MCU with your required filter specifications. NOTE: When the ADS1282 is in modulator mode, the data rate register setting will have no effect on the output MOD clock (or data rate), as this only configures the SINC filter's decimation ratio.

    As far as data rates go, the SINC filter mode will provide you with the fastest data rates, and enabling the FIR filter will reduce the output data rate (decimated by 32).

    The group delay of the SINC5 filter is flat, but the group delay will increase as you decrease the data rate. Enabling the FIR filter, you have the choice between minimum phase and linear phase. The minimum phase filter has a much lower group delay; however, this delay is frequency dependent.

     

    Dean Gacita said:
    Again looking at page 18 Table 6 of the datasheet I see if I select DR at 100 I get a data rate of 128K = 7us phase delay. Bypassing the programmable digital filter - is it correct for me to assume that would be my total group delay?

    I'm not quite sure what you mean. At the 128kSPS data rate the time between continuous conversions will be 7us; however, the first settled filter result will require ~63 conversion or 63*7us = 441us. This is assuming you are in SINC filter mode.

    By bypassing the digital filter you will get data out at the MOD clock frequency, but to use this data you will need to perform the weighted moving average, given by equation 5.

    Please NOTE: At the 128kSPS data rate the SCLK is not fast enough to clock out 32-bits of data, so you'd have to truncate the data.

     

    References:

    https://e2e.ti.com/blogs_/archives/b/precisionhub/archive/2015/01/21/delta-sigma-adc-basics-understanding-the-delta-sigma-modulator

    https://e2e.ti.com/blogs_/archives/b/precisionhub/archive/2015/02/10/delta-sigma-adc-basics-how-the-digital-filter-works

     

    Did I answer your question?

     

  • 0 in reply to Christopher Hall
    Intellectual 300 points

    Chris;

    Referring to to Figure 37 on the same page, the modulator output mode bypasses all of the internal digital filtering of the ADS1282. Instead of getting a single settled conversion result, you will get a digital bit-stream and will have to compute the value given by equation 5.

    My thoughts - After the forth or third sample Equation 5 becomes valid (within my MCU). Once in the MCU  - Y[N] is the 32 bit serial word of the value generated from the modulator samples. At that point I would implement a filter to obtain the information I am looking for.

    With this understanding I moved on to find out how long would it take to get the modulator data into the MCU. Studying Table 4 and Figure 35 it appears to me that I can get the data imported at 16*1uS?

    Is this correct?

    BTW You did answer my questions.

    Dean Gacita

  • 0 in reply to Dean Gacita
    TI__Mastermind 44610 points

    Hi Dean,

    Dean Gacita said:
    My thoughts - After the forth or third sample Equation 5 becomes valid (within my MCU). Once in the MCU  - Y[N] is the 32 bit serial word of the value generated from the modulator samples. At that point I would implement a filter to obtain the information I am looking for.

    It's not quite that simple. Y[n] is still not a 32-bit word, but rather it is a multi-bit bitstream. I made up some data just to show an example calculation:

    It is the Y bitstream now that is your data, but it doesn't provide you with any significant resolution until you've accumulated many samples and post-processed the data through a low-pass filter.

    Dean Gacita said:
    With this understanding I moved on to find out how long would it take to get the modulator data into the MCU. Studying Table 4 and Figure 35 it appears to me that I can get the data imported at 16*1uS?

    After 16 mod clocks the bitstream will be stable, but then you will need to start clocking in bits, and you'll need to clock in many bits and perform the post-processing before you have valid data. The settling time to get your first conversion result will depend on your digital filter implementation.

     

  • 0 in reply to Christopher Hall
    Intellectual 300 points

    Chris:

    Once again thanks for your input. Let me give you a larger picture on the project. I wish to use the ADS1282 in a digital control loop. As you know the measurement speed is critical for the loop to operate with any type bandwidth. If we use the digital filtering available the measurement update rate will be too slow. So my thinking is to provide the MOD data to the high speed FPGA to do the filtering. An important thought here is the data out of the ADS1282 will still only be 16uS. Any digital system would need many samples to settle out the resolution. I like the feature of moving the digital noise out to higher frequencies to be filtered out. The thing I do not know at this time is how fast the electro mechanical system needs to be updated. So I want to  offer a range from the fastest update rate to a minimum by providing all the filtering and other goodies in the ADS1282.

    If you have any thoughts on this I would like to hear them.

    Dean Gacita

  • 0 in reply to Dean Gacita
    TI__Guru**** 172646 points
    Hi Dean,

    The caveat here is that the MOD data will need to be associated with the modulator clock, which is the main clock of the ADS1282 by 4 (second paragraph, section 9.12) or 1.024 MHz based on the standard 4.096MHz. In modulator output mode, you just get the raw bit-stream of data from the first and second stages, so I'm not sure where your 16uS figure is coming from. Can you expand on that a little? Where is this value coming from?