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ADC34J43EVM: About LVDS to LVPECL DC coupled translation of SYNC pin

diverger
Expert 1195 points
Part Number: ADC34J43EVM

I don't understand well about this.

SYNCP and SYNCM of the board are intended to DC coupling with LVDS, right? But CLK and SYSREF are intended to LVPECL AC coupled, why SYNC is LVDS DC coupling? And the datasheet says the common mode voltage of SYNC pins is internally biased at 0.9V, why bias it at 0.95Vcm externally again? 

  • 0
    TI__Genius 12780 points

    Hi Diverger,

    The SYNC signal should be DC coupled because it is truly not an AC signal. SYNC gets pulled low during JESD link establishment, and stays low until the link is up (then goes high again).

    We are attempting to match the DC level of the incoming LVDS/LVPECL SYNC  signal to that of the internally biased ADC SYNC pin (If the SYNC signal were AC coupled, we wouldn't need to worry about this). This level shifting method to 0.95VDC (could also be 0.9V in accordance with datasheet) is somewhat crude, but gets the job done. If you prefer, you can use a level shifter, something like this, but would require providing the DC levels to the level shifter.

    http://www.ti.com/lit/ds/symlink/sn74avc2t244.pdf

    Best Regards,

    Dan