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DAC37J84EVM: JESD error rate

Prodigy 100 points

Replies: 8

Views: 160

Part Number: DAC37J84EVM

Hi,

I am running 12.288 GB JESD link (scrambling off) between TSW14J56 and DAC37J84EVM.

I can see the data, however, DAC GUI shows a large amount of 8b/10b errors happening and NO alignment errors. A large amount of errors causes the link to resync and the output waveform will disappear during resync.

Also, I noticed that with scrambling I am getting less 8b/10b errors (0-5000 and slowly increasing) but more alignment errors (Overall link 0 error count is less than without scrambling).

1) On the custom build board what could be done to improve the BER? 
2) From the data sheet it is not clear how to use the eye-scan. Do I need JTAG for that? Can this be done with SPI?
3) Do I need additional software to run eye-scan?

Cheers,
Anton

  • Hi Anton,

    Please advise the exact DAC37j84 mode that you are running (i.e. the front panel quick start that you have configured). We have tested these modes and don't see the 8b/10b error. We have noticed that you will sometime need to tighten the mating of the FMC connector between the two EVMs to prevent issue like this. Simply disconnect the two boards and make sure there are no dusts (or even broken FMC connection) before reconnect. This may fix this issue.

    Please also make sure to clear the alarm after initializing the board to ensure this is not a sticky error from board initialization.

    Regarding your questions:

    1. you can try to adjust your FPGA SerDes TX lanes with either FIR or pre-emphasis to optimize the eye diagram. The DAC38j84 SERDES SRX core have adaptive CTLE to compensate for the channel loss. You can also have a short reach connection between the FPGA and DAC38j84.

    2/3. you may use the app note link below to perform eye scan:

    http://www.ti.com/lit/an/slaa762/slaa762.pdf

    -Kang

  • In reply to Kang Hsia:

    Hi Kang,

    The DAC mode is shown below.

    Reconnecting the boards did not fix the issue. I noticed that the amount of errors depends on the type of the waveform send from the TSW14J56. Simpler wave forms show less errors. Also, the FMC connector is very sensitive and rotating/pressing affects the amount of errors. What else can affect the BER of the JESD link?


    Can you provide the DAC38RF8x_EYE_SCAN GUI software. Is it possible to apply "Eye Scan Testing With the DAC38RFxx" application note to DAC3XJ84? Are the steps the same?

    Anton

  • In reply to Anton Gvozdev:

    I noticed that the following setting significantly improves the BER.

    Could you please provide more information about CDR algorithms and equalisation methods. (Datasheet table 7: "See section 7.2.5.1 for further details..". There is no such chapter in the data sheet). 

  • Guru 52415 points

    In reply to Anton Gvozdev:

    Anton,

    We are looking into this.

    Regards,

    Jim

  • Guru 52415 points

    In reply to Anton Gvozdev:

    Anton,

    The software can be downloaded from the link below.

    Regards,

    Jim

    txn.box.com/.../jc86gtdri0k5odzvau2eml3p93sv26nz

  • In reply to Anton Gvozdev:

    Hello,

    Regarding 

    Anton Gvozdev
    Could you please provide more information about CDR algorithms and equalisation methods. (Datasheet table 7: "See section 7.2.5.1 for further details..". There is no such chapter in the data sheet). 

    There is a typo, it should be refer to the following section:

  • In reply to Kang Hsia:

    Thanks for that.

    Could you please provide information regarding CDR algorithms. There are 8 different regimes and it seems that all of them have different performance, but what do they do and what is the difference between them?

    Anton

  • In reply to Anton Gvozdev:

    Anton,

    We will need to know your strategy and needs in your application that requires such information. The current CDR setting has been tuned for short reach application specifically for JESD204B. This assumed synchronous SERDES between FPGA and DAC (i.e. reference clocks are synchronized)

    The CDR may need to be tuned if you are using asynchronous SERDES between FPGA and DAC. The support for the tuning for the CDR is beyond the typical data converter support, and we cannot support it on a case by case level outside of JESD204B environment. (i.e. tuning of CDR based on tracking rate and asynchronous rate of the SERDES). 

    The best I can do is refer you to the following guidelines of our CDR algorithm. The CDR algorithm and setting follows the typical CDR architecture. Please take a look. TI cannot support much further on the tuning of CDR.