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ADS62P49: Expected output mismatch in LVDS vs parallel CMOS Mode

Prodigy 70 points

Replies: 7

Views: 79

Part Number: ADS62P49

I am seeing a fixed DC offset in the output of adc when it is set in LVCMOS mode vs when it is set in LVDS output mode. When I give input as sine wave of 10dBm 1MHz frequency, the output of LVCMOS mode is centered at 0 . However, when the adc output mode  is set as LVCMOS, the output comes out above (2^13), though the shape is retained correctly. I am suspecting that the parallel LVCMOS mode is not removing the dc offset.

Also when I give no input to channel A, I am expecting the lower 2-3 bits to be triggered rest all should be 0. This is observed for LVDS mode, but in CMOS mode, 2-3 bits are triggered and rest all are fixed at HIGH.

Is there a way to overcome this issue or some register settings for ADC to be set. I have already tried 'Enable Offset Correction' for ADC but did not work.

  • Guru 56565 points


    We are looking into this.



  • In reply to jim s:


    Please see page 15 of the ADS62P49 datasheet at the link posted below. You will see that you have to selectively change the voltage applied to pins SCLK and SEN depending on which interface (LVDS or CMOS) and data format (2's complement or Offset binary) you are using. Verify that you are correctly setting the voltages as shown in Table 5 and Table 6 and verify that you get the expected results. 



  • In reply to Yusuf%20Agoro:

    Sir, thank you for the suggestion. However, I am using FMC150 card having this adc chip where I have serial controls only from fmc pinout. What I have deduced from several test cases is that even though I am selecting 2's complement format with Cmos parallel mode but cmos mode is being set correctly however it is still offset binary output bits. Hence the adc out value is varying from 0 to 2^14 and not -2^13 to +2^13. Please correct me if my inference is wrong .
  • In reply to prem dubey:


    As mentioned in the prior message, on page 15 of the datasheet, instructions are shown for how to configure in parallel mode. Have you referenced them? First sentence states that RESET must be held high for parallel mode. have you confirmed this? 


  • In reply to Yusuf%20Agoro:


    I believe the parallel configuration here refers to mode of configuring the adc register settings (either use serial pins or direct voltage on some pins to configure the modes) and not the type of output data.So what I have tried till now is serial configuration mode. For parallel mode you have suggested, what voltage should I apply on SEN for 2's compliment cmos parallel mode. And how do I apply this specific voltage using VHDL. 

    I am using zc706 carrier card

  • In reply to prem dubey:


    You can also adjust data format by properly programming register address x50. You can choose whether output data is formatted as 2's complement or offset binary as shown below. Reference page 25 of the datasheet. 


  • In reply to Yusuf%20Agoro:

    Sir below is the register settings I am doing where first two letters are hex addresses of register and last two are data of register.