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PCM1792a CBM CFS pops

Other Parts Discussed in Thread: PCM1792A

Hi


I'm working on a project that use the pcm1792a codec.


BitClock is generated by an external circuit

FrameSync clock is generated by the cpu


BitClock is always on

FrameSync arrive only when some music is played by the CPU using I2S bu

We have a spike as soon as data start to arrive to the codec. Right now IOUTL+ and IOUTL- are connected to 100Ohm resistor to undestand the problem. After this initial spike no problem come from the pcm1792a.

One idea is that we need to have both clock stable and the problem is that we generate the FrameSync only with data (there is a small pull down when the cpu put in HZ)

To overcame this problem I have used the OPE bit to delay the output but the spike just come as soon as OPE go to 0 again but in this case we have clock stable since 40 mS

- Yellow is the spi command to the codec

- green is the command that change the frequency (bit clock)

- blue is the frame sync clock

- green is analog output

So as you can see Frame sync clock is stable since 40 mS and I have a long delay to consider bitclock stable frome activation. The input is a sinusoide.

Any suggestion?

  • Hi Michael,

    Is the below interpretation of the picture correct?

    Yellow: SPI signal

    Blue: Frame Clock

    Purple: Analog output

    Green: some sort of enable?

    The spike might be caused by a DC level mismatch when the signal is enabled, before the DC offset can be corrected. Are you able to measure a DC offset on you input before the part is enabled?

    Justin

  • Green is the instant when I prepare pixel clock. DC offset measured from? Because DAC go out with current

    Michael

  • Hi Justin,

    Hi Michael.

    I'm participating to the project too and I know well the case.

    There is one more picture that is the expansion of the trace in correspondence of the spike. The image follows.

    The last played file was a sinusoidal signal of 1KHz, when the Frame Sync was interrupted, and the spike represents, as you can see, a part of a sinusoid at 1KHz, just in the point the OPE has been enabled. This means, this is my opinion, that the interruption of Frame Sync does not permit the completion of the streaming and a plain flow of pcm1792a internal registers: it will output this as garbage at starting of new streaming when OPE is enabled. We are going to generate the Frame Sync and supply it to the I2S port: this way, BCK and LRCK flow continuously and, when the sample are all zeros, pcm1792a will put its outputs in the idle condition.
    What is your opinion?

    Please note the current Frame Sync runs at 96.000Khz, but the previous was 44.100KHz, so,  that  "sinusoid garbage'" has a duration of  about one half of 1ms . The output current flows on an 100 Ohms resistor. The voltage at level zero should be 6.2mA x 100 Ohms = 0.62V, but we measure a current of 5.78 mA and we do not understand why... This is another question we'd like to fix.


  • Hi Angelo,

    I agree that if the Frame sync signal is interrupted this will cause unexpected output, so if this will happen predictable the part should be PCM1792A should be muted until the clocks are corrected.

    As for the reason that you are getting 5.78 mA out could be that to set the reference point , you need a resistor on Iref to ground. The datasheet recommends a 10K Ohm resistor to ground from Iref, this pin will effect where 0 dB will be.

    Justin

  • Hi Justin.

    Thank you very much for your answer.


    The decision we made to supply the frame-sync did solve the problem of pops at streaming starting, but we still have little pops sometimes when audio is interrupted or paused. We are investigating on that.
    We used a 10K Ohm resistor between Iref pin and ground, as the application circuit suggest, but we have 5,78mA at 0 level and we do not understand why. We will try some other resistor values to see if this current changes.