Hi
I'm working on a project that use the pcm1792a codec.
BitClock is generated by an external circuit
FrameSync clock is generated by the cpu
BitClock is always on
FrameSync arrive only when some music is played by the CPU using I2S bu
We have a spike as soon as data start to arrive to the codec. Right now IOUTL+ and IOUTL- are connected to 100Ohm resistor to undestand the problem. After this initial spike no problem come from the pcm1792a.
One idea is that we need to have both clock stable and the problem is that we generate the FrameSync only with data (there is a small pull down when the cpu put in HZ)
To overcame this problem I have used the OPE bit to delay the output but the spike just come as soon as OPE go to 0 again but in this case we have clock stable since 40 mS
- Yellow is the spi command to the codec
- green is the command that change the frequency (bit clock)
- blue is the frame sync clock
- green is analog output
So as you can see Frame sync clock is stable since 40 mS and I have a long delay to consider bitclock stable frome activation. The input is a sinusoide.
Any suggestion?