TLV320AIC3263EVM-U Digital Microphone

Dennis Kaupmann

Other Parts Discussed in Thread: TLV320AIC3254

Hello,

right now I'm trying to get one of the digital onboard microphones working on my AIC3263EVM-U Eval-Board.

In this first test I would like to route the signal of the digital mic to the headphone jack.
I'm using PurePath Studio and a sample rate of 48kHz with the following Setup.

I attached the project here:
7608.Test1.rar

Unfortunately I don't hear any sound from the microphone.
If I knock on the mic or the PCB it i get some signal but if i speak or whistle in it I don't hear any sound in the earpiece.
It seems like only the structural sound is received from the microphone.

Can anybody tell me what I'm doing wrong?
Do I have to configure the decimation filter in some kind?

Are there any examples how to use the digital mic with purepath or is it even possible to route it via Codec Control?

Thanks an lot in advance
Dennis

over 9 years ago

0 Converter Apps over 9 years ago

TI__Mastermind 28585 points

Hi Dennis,

I have asked my colleague to take a look at this.

Best Regards,

dave

0 J- over 9 years ago

TI__Mastermind 46195 points

Hi Dennis,

When you place the digital mic component, the following statement in the SystemSettingsCode becomes active:

%%if (%%prop(Include_DigMic) == 1)
    reg[100][0][60] = 0x80                 ; Enable FIFO on CIC2
    reg[0][0][112] = 0xd4; Enable CIC2 and Digital mic for Left and Right Channel
    reg[0][4][101] = 0x45     ; GPIO5 --> DigMic2 and DigMic3 data, GPIO6 --> DigMic4 and DigMic5 data
    reg[0][4][91] = 0x04      ; GPIO6 in input mode.
    reg[0][4][90] = 0x04      ; GPIO5 in input mode
    reg[0][4][87] = 0x28      ; GPIO2 is ADC_MOD_CLK
%%endif

Are these the pins that you are using?

More details on the SystemSettingsCode can be found in this wiki:

http://e2e.ti.com/support/data_converters/audio_converters/w/design_notes/2777.modifying-the-configuration-script-of-a-pps-process-flow.aspx

Regards,

J-

0 Dennis Kaupmann over 9 years ago in reply to J-

Prodigy 85 points

Hi J,

thanks for your regard.
Yes it seems like I'm using the right inputs.
The schematic of the AIC3263EVM-U shows the following connections:

GPIO2 --> CLK DigMic2-DigMic5
GPIO5 --> DATA DigMic2/DigMic3
GPIO6 --> DATA DigMic4/DigMic5

I can meassure the clock at the microphones at a frequency of 3.072MHz.
As I mentioned get some kind of signal when I knock on the mic or the PCB but it seems like the sound which is transmitted through the air is not recognized.
Do I have to set up some kind of amplification, that the airsound is amplified as is its amplitude is lower?

Or is it possible that the microphone data is sampled correctly and the problem occurs at the DAC?
I didn't change any settings at the Int8xOut Block.
I attached the Sourcecode Below.

Cheers
Dennis

Application:  PurePath Studio (Portable Audio) MiniDSP Assembler
File Name:    Z:\Software\PurePath\Test\Test1\base_main_Rate48\aic_main.lst
Date:         21.10.2014 09:37:49
Version:      version 5.95 build 1 revision 34314
Arguments:    'aic_main.asm' /image='Z:\Software\PurePath\Test\Test1\base_main_Rate48\aic_main.image'/list='Z:\Software\PurePath\Test\Test1\base_main_Rate48\aic_main.lst' /configuration='base_main_Rate48' /debug /warnings=OFF /target=AIC3263
================================================================================

Listing for file: aic_main.asm



Reg Code
========
                  line: 

                                --- File: aic_main.asm ---
                    175:  .endencrypt 
                    260:  .sync(84) 
                    283:  .sync(22) 
                    284:   
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                     49:  .codeblock registers target=regs, stream=Primary, component=AIC3263App8x4x_1 
                     50:  reg[0][0][1] = 0x01                        ; reg(0)(1)(0x00 => 0 )     S/W Reset  
                     51:  reg[0][0][4] = 0x33                        ; ADC_CLKIN = PLL_MCLK, DAC_CLKIN = PLL_MCLK 
                     52:  reg[0][0][5] = 0x00                        ; PLL_CLKIN = MCLK1 
                     53:  reg[0][0][6] = 0x91                        ; P=1, R=1 
                     54:   
                     55:  ;----------------------------------------------------------------------------------- 
                     56:  ; Clock and Interface Configuration 
                     57:  ;----------------------------------------------------------------------------------- 
                     58:  ; USB Audio supports 8kHz to 48kHz sample rates 
                     59:  ; An external audio interface is required for 88.2kHz to 192kHz sample rates 
                     60:  ;----------------------------------------------------------------------------------- 
                     61:  ; P=1, R=1, J=8; DOSR = 32 (MSB); DOSR = 32 (LSB); NADC Powerdown NADC = 2; NADC Powerup MADC = 8; AOSR = 32 
                     62:  ; P=1, R=1, J=8; DOSR = 64 (MSB); DOSR = 64 (LSB); NADC Powerdown NADC = 2; NADC Powerup MADC = 8; AOSR = 64 
                     63:      reg[0][0][7]  = 0x08             ; P=1, R=1, J=8 
                     64:      reg[0][0][13] = 0x00             ; DOSR = 128 (MSB) 
                     65:      reg[0][0][14] = 0x80             ; DOSR = 128 (LSB) 
                     66:      reg[0][0][18] = 0x02             ; NADC Powerdown NADC = 2 
                     67:      reg[0][0][19] = 0x90             ; MADC Powerup MADC = 16 
                     68:      reg[0][0][20] = 0x40             ; AOSR = 64 
                     69:   
                     70:  ; P=1, R=1, J=8; DOSR = 192 (MSB); DOSR = 192 (LSB); NADC Powerdown NADC = 2; MADC Powerup MADC = 16; AOSR = 96 
                     71:  ; P=1, R=1, J=8; DOSR = 256 (MSB); DOSR = 256 (LSB); NADC Powerdown NADC = 2; MADC Powerup MADC = 16; AOSR = 128 
                     72:  ; P=1, R=1, J=24; DOSR = 384 (MSB); DOSR = 384 (LSB); NADC Powerdown NADC = 2; MADC Powerup MADC = 16; AOSR = 192 
                     73:  ; P=1, R=1, J=16; DOSR = 512 (MSB); DOSR = 512 (LSB); NADC Powerdown NADC = 2; MADC Powerup MADC = 16; AOSR = 256 
                     74:  ; P=1, R=1, J=24; DOSR = 768 (MSB); DOSR = 768 (LSB); NADC Powerdown NADC = 2; MADC Powerup MADC = 24; AOSR = 256 
                     75:      reg[0][0][11] = 0x02             ; P=1, R=1, J=8; DOSR = 128 (MSB); DOSR = 128 (LSB); NADC Powerdown NADC = 2; NADC Powerup MADC = 8; AOSR = 128; P=1, R=1, J=8; DOSR = 192 (MSB); DOSR = 192 (LSB); NADC Powerdown NADC = 2; NADC Powerup MADC = 12; AOSR = 128; P=1, R=1, J=8; DOSR = 256 (MSB); DOSR = 256 (LSB); NADC Powerdown NADC = 2; NADC Powerup MADC = 16; AOSR = 128; P=1, R=1, J=24; DOSR = 384 (MSB); DOSR = 384 (LSB); NADC Powerdown NADC = 2; NADC Powerup MADC = 24; AOSR = 128; P=1, R=1, J=16; DOSR = 512 (MSB); DOSR = 512 (LSB); NADC Powerdown NADC = 2; NADC Powerup MADC = 32; AOSR = 128; P=1, R=1, J=24; DOSR = 768 (MSB); DOSR = 768 (LSB); NADC Powerdown NADC = 2; NADC Powerup MADC = 48; AOSR = 128; NDAC = 2, divider powered off 
                     76:  ; NDAC = 2, divider powered on 
                     77:  reg[0][0][8] = 0x00                        ; D=0000 (MSB) 
                     78:  reg[0][0][9] = 0x00                        ; D=0000 (LSB) 
                     79:  reg[0][0][12] = 0x88                       ; reg(0)(0)(0x0c => 12)     DAC Powerup MDAC = 8 
                     80:  reg[120][0][50] = 0x88                     ; Interpolation Ratio is 8, FIFO = Enabled 
                     81:  reg[100][0][50] = 0xa4                     ; Decimation Ratio is 4, CIC AutoNorm = Enabled, FIFO = Enabled 
                     82:   
                     83:  reg[0][0][60] = 0x80                       ; reg(0)(0)(0x3c => 60)     DAC prog Mode, DAC & ADC filter engines powered up together                           
                     84:  ; reg(0)(0)(0x3c => 60)     DAC prog Mode, DAC & ADC filter engines not powered up together                           
                     85:  reg[0][0][61] = 0x00                       ; reg(0)(0)(0x3d => 61)     ADC prog mode 
                     86:  reg[0][0][83] = 0x0                    ; adc vol control = 0db 
                     87:  reg[0][0][84] = 0x0                    ; adc vol control = 0db 
                     88:   
                     89:  reg[0][1][1 ] = 0x00                       ; reg(0)(1)(0x01 => 0 )     Crude avdd disabled 
                     90:  reg[0][1][3 ] = 0x00                       ; reg(0)(1)(0x03 => 3 )     LDAC FIR 
                     91:  reg[0][1][4 ] = 0x00                       ; reg(0)(1)(0x04 => 4 )     RDAC FIR 
                     92:  ;reg[0][1][11] = 0x35                       ; reg(0)(1)(0xB  =>11 )     DePop HP 
                     93:  reg[0][1][31] = 0x80                       ; reg(0)(1)(0x1F =>31 )     HP in ground Centered mode; HPL gain 0 dB 
                     94:  reg[0][1][32] = 0x00                       ; reg(0)(1)(0x20 =>32 )     HPR independent gain 0 dB 
                     95:  reg[0][1][33] = 0x28                       ; reg(0)(1)(0x21 =>33 )     Charge pump runs on Osc./4 
                     96:  reg[0][1][34] = 0x33 ;0x3e                       ; reg(0)(1)(0x22 =>34 )     Set CP mode 
                     97:  reg[0][1][35] = 0x10                       ; reg(0)(1)(0x23 =>35 )     Power up CP with HP 
                     98:  reg[0][1][52] = 0x40                       ; reg(0)(1)(0x34 => 52)     ADC IN1_L is selected for left P 
                     99:  reg[0][1][54] = 0x40                       ; reg(0)(1)(0x36 => 54)     ADC CM1 is selected for left M 
                    100:  reg[0][1][55] = 0x40                       ; reg(0)(1)(0x37 => 55)     ADC IN1_R is selected for right P 
                    101:  reg[0][1][57] = 0x40                       ; reg(0)(1)(0x39 => 57)     ADC CM1 is selected for right M 
                    102:  reg[0][1][121] = 0x33                      ; reg(0)(1)(0x79 => 121)    Quick charge time for Mic inputs 
                    103:  reg[0][1][122] = 0x01                      ; reg(0)(1)(0x7A => 122)    Vref charge time - 40 ms. 
                    104:   
                    105:  PROGRAM_MINIDSP_A  
                    106:  PROGRAM_MINIDSP_D 
                    107:   
                    108:   ; adaptive mode for ADC; adaptive mode for DAC 
                    109:  ;IADC  = 1024        ;  
                    110:  ;IDAC  = 1024        ; 
                    111:   
                    112:      ;IDAC  = 256    ; MDAC*DOSR;IADC  = 256    ; MADC*AOSR;IDAC  = 512    ; MDAC*DOSR;IADC  = 512    ; MADC*AOSR;IDAC  = 1024    ; MDAC*DOSR 
                    113:      ;IADC  = 1024    ; MADC*AOSR 
                    114:      reg[100][0][48] = 4 
                    115:      reg[100][0][49] = 0 
                    116:      reg[120][0][48] = 4 
                    117:      reg[120][0][49] = 0 
                    118:  ;IDAC  = 1536    ; MDAC*DOSR;IADC  = 1536   ; MADC*AOSR;IDAC  = 2048    ; MDAC*DOSR;IADC  = 2048   ; MADC*AOSR;IDAC  = 3072    ; MDAC*DOSR;IADC  = 3072   ; MADC*AOSR;IDAC  = 4096    ; MDAC*DOSR;IADC  = 4096   ; MADC*AOSR;IDAC  = 6144    ; MDAC*DOSR;IADC  = 6144   ; MADC*AOSR 
                    119:   
                    120:   
                    121:  reg[0][0][63] = 0xc2                       ; reg(0)(0)(0x3f => 63)     DAC L&R DAC powerup Ldata-LDAC Rdata-RDAC (soft-stepping disable) 
                    122:  reg[0][0][64] = 0x00                       ; reg(0)(0)(0x40 => 64)     DAC Left and Right DAC unmuted with indep.  vol. ctrl 
                    123:  reg[0][0][81] = 0xd6                      ; reg(0)(0)(0x51 => d6)     ADC Powerup ADC left and right channels in Digital mode(soft-stepping disable) 
                    124:  reg[0][0][82] = 0x00                       ; reg(0)(0)(0x51 => 81)     ADC Powerup ADC left and right channels (soft-stepping disable); reg(0)(0)(0x52 => 82)     ADC Unmute ADC left and right channels,L,R fine gain=0dB 
                    125:   
                    126:  reg[0][1][27] = 0x33                       ; reg(0)(1)(0x1B =>27 )     LDAC -> HPL, RDAC -> HPR; Power on HPL + HPR 
                    127:  reg[0][1][59] = 0x00                       ; reg(0)(1)(0x3b => 59)     ADC unmute left mic PGA with 0 dB gain 
                    128:  reg[0][1][60] = 0x00                       ; reg(0)(1)(0x3c => 60)     ADC unmute right mic PGA with 0 dB gain 
                    129:   
                    130:  reg[0][4][1]  = 0                          ; ASI1 Audio Interface = I2S 
                    131:  reg[0][4][10] = 0                          ; ASI1 Audio Interface WCLK and BCLK  
                    132:  reg[0][4][8]  = 0x50                       ; ASI1 Left DAC Datapath = Left Data, ASI1 Right DAC Datapath = Right Data 
                    133:  reg[0][4][23] = 0x05 ; ASI2_IN_CH<L1,R1> = miniDSP_A_out_ch<L2,R2> 
                    134:  reg[0][4][24] = 0x50 ; ASI2_OUT_CH<L1> = Channel<L1> ; ASI2_OUT_CH<R1> = Channel<R1> 
                    135:  reg[0][4][39] = 0x06 ; ASI3_IN_CH<L1,R1> = miniDSP_A_out_ch<L3,R3> 
                    136:  reg[0][4][40] = 0x50 ; ASI3_OUT_CH<L1> = Channel<L1> ; ASI3_OUT_CH<R1> = Channel<R1> 
                    137:   
                    138:  reg[100][0][20] = 0x00 ; Disable ADC double buffer mode 
                    139:  reg[120][0][20] = 0x00 ; Disable DAC double buffer mode 
                    140:  ; Enable ADC double buffer mode; Enable DAC double buffer mode 
                    141:      reg[0][0][11] = 0x82                   ; NDAC = 2, divider powered off 
                    142:      reg[100][0][60] = 0x80                 ; Enable FIFO on CIC2 
                    143:      reg[0][0][112] = 0xd4; Enable CIC2 and Digital mic for Left and Right Channel 
                    144:      reg[0][4][101] = 0x45     ; GPIO5 --> DigMic2 and DigMic3 data, GPIO6 --> DigMic4 and DigMic5 data 
                    145:      reg[0][4][91] = 0x04      ; GPIO6 in input mode. 
                    146:      reg[0][4][90] = 0x04      ; GPIO5 in input mode 
                    147:      reg[0][4][87] = 0x28      ; GPIO2 is ADC_MOD_CLK 
                    148:   
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                                --- File: aic_gen.asm ---
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                    941:  .codeblock Registers2 target=regs, stream=Primary, component=DigMic4xIn_1 
                    942:  reg[0][0][82] = 0 
                    943:   
                    944:  ; Left channel AGC initialization 
                    945:  reg[0][0][83] = 0 
                    946:  reg[0][0][86] = 32 
                    947:  reg[0][0][87] = 254  
                    948:  reg[0][0][88] = 0 
                    949:  reg[0][0][89] = 104 
                    950:  reg[0][0][90] = 168 
                    951:  reg[0][0][91] = 6 
                    952:  reg[0][0][92] = 0 
                    953:   
                    954:  ; Right channel AGC initialization 
                    955:  reg[0][0][84] = 0 
                    956:  reg[0][0][94] = 32 
                    957:  reg[0][0][95] = 254  
                    958:  reg[0][0][96] = 0 
                    959:  reg[0][0][97] = 104 
                    960:  reg[0][0][98] = 168 
                    961:  reg[0][0][99] = 6 
                    962:  reg[0][0][100] = 0 
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0 errors detected

0 Dennis Kaupmann over 9 years ago in reply to Dennis Kaupmann

Prodigy 85 points

Kind of weird,

I attach an external PDM microphone from STMicroelectronics (MP34DT01) on the same input and it's working.

Looks like something is wrong with the onboard microphones :-/
On the oscilliscope it looks like the timing of the data channel of the knowles onboard mic doesn't fit the clock channel.
Is there anything I can do about it?

Cheers
Dennis

0 J- over 9 years ago in reply to Dennis Kaupmann

TI__Mastermind 46195 points

HI Dennis,

There is no fine tune of the PDM input timing. Do you have the part number for the knowles microphone?

Thanks,

J-

0 Dennis Kaupmann over 9 years ago in reply to J-

Prodigy 85 points

Hi,

sorry for the late reply.

I tried to use the Knowles onboard microphones (SPM0423HD4H-WB)
With the ST Microphones (MP34DT01) its working without any problems.

Cheers
Dennis

0 J- over 9 years ago in reply to Dennis Kaupmann

TI__Mastermind 46195 points

Hi Dennis,

The mic needs to setup the data 20ns or more before the clock edge transition is complete and hold it for 3 ns after the transition.

Regards,

J-

0 Bruce Ploetz over 9 years ago in reply to Dennis Kaupmann

Prodigy 130 points

I am trying to use the Knowles SPK0415 with a TLV320AIC3254 and I get nothing but zeroes out of the ADC. I have used SPM0423HM4H with no problems in the same setup. Hope someone has some answers on this one. I have checked settings on register 0-52, 0-55, 0-25,26,27 and 0-81. All seems to be set up, I see signal and clock on the microphone, but no audio from the ADC, even from a probe point connected directly to the Dec4xIn.

0 J- over 9 years ago in reply to Bruce Ploetz

TI__Mastermind 46195 points

Hi Dennis,

I now understand what you mean. I thought you were referring to a custom board, but you are referring to the onboard mics on the EVM.

Could you probe C82 on both sides? We should expect GND on one side and IOVD1 on the other side, but want to double confirm.

Thanks,

J-

0 J- over 9 years ago in reply to Bruce Ploetz

TI__Mastermind 46195 points

Hi Bruce,

Is the setup exactly the same for both microphones? If you are using wires, make sure you twist them and signal integrity at the AIC3254 pins is proper for CLK and DATA.

Regards,

J-

0 Bruce Ploetz over 9 years ago in reply to J-

Prodigy 130 points

I am using wires now, the successful earlier system had the mics mounted on a 4 layer board. What was giving me the problem with the new mics was this paragraph in http://www.ti.com/lit/an/slaa408a/slaa408a.pdf page 33:The digital-microphone mode can be selectively enabled for only-left, only-right, or stereo channels. When
the digital microphone mode is enabled, the analog section of the ADC can be powered down and
bypassed for power efficiency. The AOSR value for the ADC channel must be configured to select the
desired decimation ratio to be achieved based on the external digital microphone properties.
I took that to mean that bit 7 on page 0 reg 81 should be zero, but when I looked at my old code it was a one. I don't know how to "power down the analog section of the ADC" otherwise. Once I turned it on I got sound but it has a scratchy mosquito noise in the background. There is a lot of RF flying around this system with Bluetooth and other radios, so maybe even the shielded twisted quad wire I am using is not good enough. Or maybe the clock derived by the PLL from the Bluetooth module i2s interface is not stable enough.
But at any rate, the Knowles mics do work, especially the one mentioned by the originator of this thread. I got very good sound out of that microphone when I had it mounted on a board.

0 J- over 9 years ago in reply to Bruce Ploetz

TI__Mastermind 46195 points

Hi Bruce,

See attached example for a 44.1k digital mic. Note that this script does not enable the analog LDO, so you might need to modify the script to do so if your system uses it.

2818.DIGMIC_44100_KHZ.txt

###############################################
#
# Digital Microphone Script
#
###############################################



###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################



###############################################
# Clock and Interface Settings
# ---------------------------------------------
# The codec receives: MCLK = 11.2896 MHz,
# WCLK = 44.1 kHz
###############################################
#
# Select Page 0
w 30 00 00
#
# PLL_clkin = MCLK, codec_clkin = PLL_CLK,
# PLL on, P=1, R=1, J=8, D=0000
w 30 04 03 91 08 00 00
#
# NDAC = 2, MDAC = 8, dividers powered on
w 30 0b 82 88
#
# DOSR = 128
w 30 0D 00 80
#
# NADC = 2, MADC = 16, dividers powered on
w 30 12 82 90
#
# AOSR = 64
w 30 14 40
#
###############################################



###############################################
# Configure Power Supplies
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
w 30 02 00
#
# Set the input power-up time to 3.1ms (for ADC)
w 30 47 32
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################



###############################################
# Configure Processing Blocks
###############################################
#
# Select Page 0
w 30 00 00
#
# PRB_P2 and PRB_R2 selected
w 30 3C 02 02
#
################################################
# High-pass second order Butterworth2 filter,
# fc = 80 Hz
###############################################
#
# Write to Buffer A:
#
# BIQUAD A, Left Channel (Page 8, Register 36, C7-C11)
w 30 00 08
w 30 24 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
#
# BIQUAD A, Right Channel (Page 9, Register 44, C39-C43)
w 30 00 09
w 30 2c 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
#
# Write to Buffer B:
#
# BIQUAD A, Left Channel (Page 26, Register 36, C7-C11)
w 30 00 1A
w 30 24 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
#
# BIQUAD A, Right Channel (Page 27, Register 44, C39-C43)
w 30 00 1B
w 30 2c 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
#
###############################################




###############################################
# Configure ADC Channel
###############################################
#
# Select Page 0
w 30 00 00
#
# Configure MISO as clock output for DIGMIC
w 30 37 0E
#
# LADC and RADC enabled for DIGMIC
# Route SCLK as DIGMIC_DATA
# Power up LADC/RADC
w 30 51 DC
#
# Unmute LADC/RADC
w 30 52 00
#
###############################################

The ADC power-up register bits automatically powers the analog front-end, ADCs and miniDSP_A (or PRB_Rx). When digital mic mode is used, the analog front-end and ADC modulator will shut down automatically to save power. However, you still need to keep the ADC power-up bits as '1' to power the ADC decimation filters and processing.

Regards,

J-

Audio

Audio forum

TLV320AIC3263EVM-U Digital Microphone