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PCM5142/PCM5242 DAC clock source

Other Parts Discussed in Thread: PCM5242, PCM5142, PCM5122

Hi!

We have an application with a PCM5142 as I2S master. I finally managed to get it working using a forum post describing clocking for the PCM5122 and later found the data sheet for the PCM5242, which seems to describe the same things much better. I assume that the clocking works the same in PCM5122, PCM5142 and PCM5242? Are they perhaps fully register compatible? Anyway, there are still some gray areas in the PCM5242 data sheet.

What I would like to do, is to connect an external clock on a GPIO, use that as input to the PLL, output the PLLOUT/4 clock on some other GPIO and route that back (externally) to the SCK pin. That part works nicely. However, when the original external clock is already a good SCK, I would like the external clock to used directly as DAC reference, thus avoiding PLL gitter in the output whenever this is possible.

Looking at the clock diagram in the data sheet of both the PCM5142 and the PCM5242, this seems possible. In the diagram, the DAC Clock Source MUX has an input named GPIO. However, in the register description, SDAC (register 14, page 0) does not list GPIO as an option. Comparing to how SREF works (register 13, page 0) for the PLL, I also imagine that some other register is used to select which GPIO pin is actually used as DAC source. Or are the clocking trees simply wrong, and there is no possibility to use a GPIO pin as SDAC?

Cheers,
Peter

  • Hi, Peter,

    Sorry for the delay in getting back to you.

    As you correctly surmised, these devices all come from the same family, so the register sets are very similar.

    For your specific questions, I am not sure at that level of detail, and the guys who support this device are out for the holidays. I will highlight this post to them so they can get back to you.

    -d2
  • Hi again.

    Some experimentation suggests that SDAC (register 14, page 0) should perhaps be 5 (101b) for GPIO input to the DAC and that the GPIO pin is selected in register 16, page 0, which is perhaps working similar to GREF (register 18, page 0).

    Please confirm and/or fill in the blanks in the spec.

    Cheers,
    Peter
  • When will I get an answer? The weeks go by, and it seems like a simple enough question.

    I.e, can I use the same GPIO pin as input to both the DAC and the PLL (without the PLL jitter being passed on to the DAC), and how do I program the registers if that is possible?

    Time is running out...

    Cheers,
    Peter
  • Hi Peter,

    I apologize for the delay, this is indeed possible. As Don stated above the register sets are similar across the PCM5xxx series. For the clock tree registers you can reference the PCM5242 data sheet. To change the clock source of the DAC you must first enable changes in the clock tree by writing to the clock flex registers (63 and 64 on page 253). You then can use register 14 (detailed in the PCM5242 data sheet) to change the DAC clock source.

    Justin
  • Hi Justin,

    But, register 14 in the PCM5242 spec (page 84) does not list GPIO as a source for the DAC. It only lists MCK (SCK or PLL), PLL, BCK and SCK, but figure 68 (the clock distribution tree, page 47) suggests that a GPIO pin can indeed be used for DAC input. So, something is either incomplete or wrong in the PCM5242 spec. My question is how I select GPIO as source for the DAC? And how do I select which GPIO pin will be used?

    Cheers,
    Peter
  • Hi Peter,

    There is a way to do this and we do need to revise the data sheet to show these options. To enable the DAC clock to be run from a GPIO input you can do the following:

    1. Enable the Flex clock registers on page 253
    2. Set Register 14 page 0 to 101.
    000: Master clock (PLL/SCK and OSC auto-select)
    001: PLL clock
    010: Reserved
    011: SCK clock
    100: BCK clock
    101: GPIO (selected using page 0/register 16)
    others: Reserved (muted)
    3.Set register 16 page 0 to the correct GPIO selection for the DAC clock mux
    000: GPIO1
    001: GPIO2
    010: GPIO3
    011: GPIO4
    100: GPIO5
    101: GPIO6
    others: Reserved (muted)

    Justin
  • This was exactly as I guessed from my experiments, cool. Thank you very much for the confirmation!

    Cheers,
    Peter