PCM1865-Q1 issues

Hi Chakravarthy,

I apologize for the trouble this has caused you and yes there is not enough info on the TDM mode in the data sheet. We are working to correct this and add further information to the data sheet about timing and how to configure the part to use TDM mode. We are also working on the GUI to provide a better register output for coefficients and how to write them. Thank you for pointing out your troubles to us as it allows us to review and improve our collateral to make our parts easier to use.

Justin

Hi Justin,

Thanks for responding quickly. Appreciate we'll soon have an update.

In the meantime if you have a 'draft' version of the timing waveform please e-mail me as it would help in my driver software works and I need not wait till official version release.

Also, there's no info on how DOUT2  pin is configured (to get all the 4-channel I2S data out from the device). The pin details on the datasheet simply does n't mention about this DOUT2 pin at all.

And in Page-31 of the datasheet, in Table-10 listing column-9 heading should be for DSP2 Clock(MHz) 2Ch and not for DSP1 Clock I guess.

About EVM :

Does the EVM configure the device correctly for TDM modes when it is selected in the GUI? How do I get all four channel I2S data out in the EVM?

With the EVM, when I configure the device for 4 or 6 ch TDM in Master mode (with proper clcoks etc applied to device), I don't get the correct data from PCM1865 (I capture the DOUT, LRCLK, BCLK etc from the device in a LA)

Hi Chakravarthy,

I will be verifying the TDM mode, and its configurations by the end of this week and will share what I find with you.
-DOUT2 can be selected as one of the options for the GPIO pins.
-As for Table 10, I will have to look more into this.
-When selected in the GUI, the drop down option TDM will only effect the FMT bits of register 0x0B.
-When in TDM mode the clocks must be set up that BCK is 256FS, with your statement of proper clocks I assume this is what you mean?

I will get back to you when I have more information.

Justin

Hi Justin,

On BCLK :

Yes, I apply 256*Fs clock (ie 12.288MHz xtal generated clock with 48KHz Fs) to the device SCKI pin externally with PCM1865 set as a master.

I configure the PLLs etc (in Purepath console GUI) and verify that all ADC & DSP clocks are as required with this external SCKI.

I get only 2 ch I2S output on DOUT pin and there's no output on DOUT2. I did configure the GPIOs (GPIO0,1 etc) earlier to output DOUT2

but still nothing happens on these pins. Is there any register to be set to enable the outputs on DOUT2 pin?

In GUI I select I2S 2-ch mode, ch-1 L&R  I get on DOUT pin but Ch-2 L&R not available on DOUT2 or GPIO pins.

The same case when I set for TDM modes (4-Ch & 6-Ch etc). I see no correct TDM data coming on DOUT either in TDM modes.

Right now for me ,the device needs to output all 4-ch data in I2S mode at least if not in TDM mode for time being but all that I get is only two channels in I2S mode.

Please advise me how to setup the device (in PCM1865-Q1 EVM board) to get all these 4-channels data.

I can tap off the signals directly from the device outputs (ie test points DOUT, LRCLK, BCK, SCKI etc) to capture with my DSP.

(Currently I could capture 2-ch data in I2S mode well).

Thanks.

Chakravarthy

Hi Chakravarthy,

I apologize for the delay, but I have done some testing and have made a post () explaining how to put a PCM186X into TDM mode. It seems that in master mode you must keep the part in 50% LRCK mode, as the pulse will freeze the output. 

As for DOUT2 you can enable this on output GPIO0 - GPIO3 in the GPIO block in the GUI by setting them to output, then selecting DOUT2.

Justin

Hi Justin,

Thanks for the reply.

I know with all the constraints you might have, you are doing an outstanding support for the customer's technical issues and I really appreciate it.

I did see this post earlier and aware of the problems with LRCK pin.

When we put the device in LRCK 1/256 duty cycle mode, the DOUT freezes and no data is output from the device. It only works when we select 50% duty cycle.

Unfortunately this mode of working for LRCK is not suitable for my application. In TDM mode, I need to have a pulse with 1/256 duty cycle in order to get the device working.

I was able to check DOUT2 on a GPIO pin and that works fine.

one more question though:

Is it possible to by-pass the mixer completely and get the analog inputs (mono-4 channels in all) to the ADCs directly?

For Beamforming application, I need to maintain the phase information between the channels precisely and do not want them to be altered via mixer, so would like to by-pass it if possible but I don't see any register setting which would make it possible.

Chakravarthy

Hi Chakravarthy,

Thank you for the compliment, I am doing my best to juggle all the requests. I appreciate your patience.

As for the signal path, the mixer cannot be removed from the signal path. All ADCs will sample at the same time and be passed through the mixer in the same way, so inputting the same signal on all 4 inputs will get you the same output on all 4 channels. I believe this will conserve the phase relationship between all 4 channels.

Could you elaborate as to why a 50% LRCK will not suffice for your system. My understanding of most TDM systems is that the rising edge of the frame clock is what would matter to each device. Is this not the case with your system, and is there a reason why the PCM186X is the master and not the host processor for the TDM bus?

Justin

Hi Justin,

The DSP I am using (non-TI device) supports many modes including multichannel TDM with master & slave clocking. But there are many caveats in getting it to work with DMA properly when the codec device is not outputting 32-bit data and Frame Synch pulse is non-standard with no timing details of the TDM mode available from the datasheets.

While it is not impossible, I have to completely re-write all the driver software, test and debug in order to get it to work with these issues and that's going to take up few weeks of time and efforts.

Since PCM1865 has such a versatile PLL, I would like to use it to generate all the required clocks and that's the reason I prefer it to be the master device.

Otherwise I have to have all these clocks generated externally with limited DSP resources since most of them have already been used up.

Chakravarthy