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PCM1774 Audio data timing

Wim Konings
Prodigy 200 points
Other Parts Discussed in Thread: PCM1774

Dear,

I'm trying to generate a 2 KHz beep on the PCM1774 but the sine wave is disturbed (see channel 1). What can cause this mismatched signal?

The audio data format is I2S, no de-emphasis filter and oversampling on.

I have set a sample rate of 8 KHz (this is also the LRCK). I'm generating  a 2 MHz (256 * fs) system clock and using the SPI bus for sending the data bytes at 1 MHz (128 * fs). The DAC is set in slave mode (for receiving LRCK and BCK). The image underneath is showing DIN on channel 1 and BCK on channel 2. The value written is 0x7FFF.

The image underneath shows LRCK on channel 1 and BCK on channel 2. There is a gap of 3.68 us between the 2 signals. Can this be the cause?

According the datasheet there must be (minimum? or exact?) 1 period of BCK signal before setting the data in I2S mode.

Best regards

Wim

  • 0
    TI__Mastermind 27880 points
    Hi Wim,

    This looks like a data issue, for I2S, the data should start at exactly 1 BCK delay after the LRCK edge. Another thing is that your BCK should always be running, but in your second scope shot it is not. Is the System clock synchronous with the BCK and LRCK?

    The waveform shown suggests an error with the data from cutting off the MSBs, which points to a clocking issue. Unless the data itself is corrupted.

    Justin
  • 0 in reply to Justin Bohr
    Prodigy 200 points

    Hello Justin,


    Thanks for the support. It looks like the processor I'm using isn't capable of achieving the timing of the LRCK and BCK clock.  I was hoping to use the SPI controller of the processor for BCK but it is started too late (3.8 us) after LRCK.

    I think I have to solve this by adding an extra PIC processor that shall take care of the audio part i.s.o. the current processor which is main task is wireless communication.

    Best regards

    Wim