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TLV320AIC3204 - Audio codec register settings for mono differential headphone

Suresha N S
Expert 1070 points
Other Parts Discussed in Thread: TLV320AIC3204

Hi all,

We are using TLV320AIC3204 in one of our designs.

We have connected mono differential 20mW speaker on the HPL & HPR lines of the codec. We have configured the audio codec in slave mode , with master providing the WCLK of 8KHz & BCLK of 256KHz (16 bit mode). We are receiving mono audio in PCM format from the Master.

After configuration, we are hearing constant noise which changes slightly in accordance to the input digital data.

Below are the register configuration we are using :

RESET:

# Select Page 0

W 30  00  00 

# Enable Self clearing software reset

W 30  01  01

 

CLOCK SETTINGS:

 

# MCLK pin is input to PLL; BCLK pin is CODEC_CLKIN

W 30  04  01

# PLL OFF ; P Value = 1 ; R Value = 1

W 30  05  11

# J Value =4

W 30  06  04

# D Value MSB=0

W 30  07  00

# D Value LSB=0

W 30  08  00

# NDAC divider powered up with value = 1

W 30  0B  81

# MDAC divider powered up with value = 1

W 30  0C  81

# DAC OSR MSB = 0

W 30  0D  00

# DAC OSR LSB = 32

W 30  0E  20

# NADC divider powered up with value = 1

W 30  12  81

# MADC divider powered up with value = 1

W 30  13  81

# ADC Oversampling Value =32

W 30  14  20

 

I2S SETTINGS:

# Audio Interface = RJF ; Data Word length = 16 bits ; BCLK and WCLK are input to the device ; DOUT will not be high impedance while Audio Interface is active

W 30  1B  20

#Data Offset Value = 0 BCLK’s

W 30  1C  00

#DAC Signal Processing Block PRB_P8

W 30  3C  08

 

POWER SETTINGS:

 

#  Select Page 1

W 30  00  01

# Disabled weak connection of AVDD with DVDD

W 30  01  08

# AVDD LDO Powered down

W 30  02  00

# Reference will power up in 40ms when analog blocks are powered up

W 30  7B  01

 

HEADPHONE SETTINGS:

 

#  Select Page 1

W 30  00  01

# HPL not routed to INL1 ; Left Channel DAC reconstruction filter's positive terminal is routed to HPL ; MAL and MAR output s are ot routed to HPL

W 30  0C  08

#Left and RIGHT Channel DAC reconstruction filter's negative terminals are not routed to HPR ; IN1R  and MAR are not routed to HPR ; HPL output is routed to HPR (use when HPL and HPR output is powered by AVDD)

W 30  0D  01

# HPL and HPR are powered up ; LOL and LOR is powered down ; Left and Right Mixer Amplifier (MAL and MAR) are powered down

W 30  09  30

# HPL driver gain is 24dB

W 30  10  18

# HPR driver gain is 24dB

W 30  11  18

 

DAC SETTINGS:

# Select Page 0

W 30  00  00

# Left DAC Channel Digital Volume Control = 0.0dB

W 30  41  00

# RIGHT DAC Channel Digital Volume Control = 0.0dB

W 30  42  00

# Left DAC Channel Powered Up ; Right DAC Channel Powered Down ; Left DAC data is Mono Mix of Left and Right Channel Audio Interface Data              Right DAC data is disabled ; Soft-Stepping is disabled

W 30  3F  B2

# When Right DAC Channel is powered down, the data is zero. ; Auto Mute disabled ; Left DAC Channel not muted ; Right DAC Channel muted ; Left and Right Channel have independent volume control

W 30  40  04

Are we missing configuration of any other registers ? Please suggest.

Looking forward to your response.

Thanks,

Suresha N S

  • 0
    TI__Guru* 84915 points

    Hi Suresha,

    I will review your registers configuration and I will answer you as soon as possible.

    Thank you.

    Best regards,

    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    TI__Guru* 84915 points

    Hi Suresha,

    Sorry for the late response.

    Regarding the register 0x3F (Page 0), left DAC is configured as "Left DAC data is Mono Mix of Left and Right Channel Audio Interface Data". Are you mixing both channels as a mono mix? Have you tried with the "Left DAC data Left Channel Audio Interface Data" configuration?

    Thank you.

    Best regards,

    Luis Fernando Rodríguez S.

  • 0 in reply to Luis Fernando Rodriguez S.
    Expert 1070 points

    Hi ,

    We were able to bring up the headphone output. 

    Actual issue was with respect to the clock configurations. 
    We were not matching the required 2.8MHz < DOSR * DAC_FS < 6.2MHz.
    We changed the clock tree to satisfy this requirement & were able to hear the audio out on Headphone.

    Also, we changed the audio routing configuration to "Left DAC data  Left channel audio interface data". This helped us to improve the audio out quality.

    Thanks for your suggestion.

    Regards,
    Suresha N S