clock setup differs from EVM-K board and real design

LostElectron

Other Parts Discussed in Thread: TLV320AIC3254

Hello,

I used the AIC3254 evaluation board (EVM-K) control sotware to help me in deifning the correct setup for the clocks dividers

I have a crystal on my design that is exactly 12.288 Mhz that is feeding the codec mclk pin.

I have BCLK and WCLK set as outputs.

No I need on my design a 8Khz sampling rate.

But if apply what the EVM control software suggest I get exactly 2x expected frequency so 16Khz.

To get exactly 8khz I need to use the setup as it is described in the enclosed picture.

So I would have a simple question: What's occurring here ?

over 8 years ago

0 J- over 8 years ago

TI__Mastermind 46195 points

Hi,

Use NDAC = 1, MDAC = 2, DOSR = 768, NADC = 1, MADC = 12, AOSR = 128. More details are in the Design and Configuration Guide app note in the TLV320AIC3254 web page.

Regards,

J-

0 LostElectron over 8 years ago in reply to J-

Prodigy 180 points

Thanks for this. All is correct right now in term of clocks frequencies.
After creating a simple DIN/DOUT loopback outside the codec I observ now a terrible audio noise/crackles coming out to headphones.
In the other way I have checked that some generated tones to DOUT are clear, so I suspect the problem could be an issue from the ADC part.
So simple question:
Does those setttings could alter in some way the ADC performance ? Thanks.
(FYI: I am using a I2S common audio bus with offset shared between 3x3254 devices)

0 J- over 8 years ago in reply to LostElectron

TI__Mastermind 46195 points

Hi,

Try the loopback feature mentioned in this wiki page: e2e.ti.com/.../2740.where-can-i-find-example-scripts-for-these-codecs

Regards,
J-

Audio

Audio forum

clock setup differs from EVM-K board and real design