tlv320aic3110 harmonics

Hi, Diego,

Welcome to E2E and thank you for your interest in our products!

In order to improve the headphone output performance, it is suggested to add a low-pass filter of 100-ohm and 47nF. Also, the output should be AC-coupled with a 47uF capacitor. Then, you should reduce the noise issues in the board. Please follow the below wiki article indications:

e2e.ti.com/.../3377.common-noise-issues-in-codecs

Please let me know if the problem persists.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis thank for your answer

I have a 47uF decoupling capacitor on the HP output

I can't use low pass filter becouse the end product needs to reproduce pure tone at 1, 2, 3, 4, 5, 6, 7 and 8 Khz so I can't low pass filter 1 khz harmonics

I'm trying to isolate the source of the armonics

I saw that you publish a new version of AIC3110 codec and add some good information

I saw you add 22uF on each power pin and I have not those caps Could my problem be related to this?

I saw that you specify a power supplies sequence and I have all PS starting at the same time Could my problem be related to this?

I saw that you recomend a special ground conection from analog to digital ground plane I have a unique power plane Could my problem be related to this?

I use an stm32f411 (arm cortex m4 with fpu) to control the codec by I2S I use mclk generated by my uC to feed mclk input of the TLV becouse of my uC PLL and frequency generation block I have a litle error on the output frecuency (I can generate 44108 Hz insted of 44100 Hz on WS and the same error n the BCLK and mclk signa) I try with codec PLL and without codec PLL and always get the same harmonics level Could my problem be related to this?

I generate sine wave using cmsis dsp library (https://github.com/mikeferguson/stm32/blob/master/libraries/CMSIS/DSP_Lib/FastMathFunctions/arm_sin_f32.c) I'm using 32 bits floaitng point variables to generate sin waveform and then converted to 32 bits integer to feed I2S stream Could that function and that convertion (floating point to integer) be the source of my problem?

Harmonics are measured with a digital oscilloscope and their embedded FFT function in the HP output pin (before decoupling capacitor)

I would like to reproduce the method that you are using to especify THD on datasheet using TLV320aic3110 evaluation board Could you tell me how do I do to get the same THD that is on DS?

I really need this audio code to work with a THD less that 0,1% becouse I already invest 2 year of development on this proyect So if you think that this audiocodec can't work with that thd please let me know ASAP

Thank!

Hi, Diego,

In order to get the best performance of the device, there are several points that you should ensure in your board.

First of all, the decoupling capacitors must be placed in power supplies as close as possible. The noise issues in outputs pins are often related with power supplies issues. These capacitors will ensure that there won't be any parasitic signals at power supplies and then in the outputs. So, please add the suggested capacitors at power pins.

The ground separation is also important to reduce the digital noise at analog outputs/inputs. If this separation is not possible, please ensure that the digital activity is far of analog activity. Also, it is possible to reduce the noise when digital signals are surrounded by ground lines/plane.

All the datasheet values are measured with an A-weighted filter and a low-pass filter at the outputs. As I mentioned, a 20KHz low-pass filter should be added for measurement purposes. Could you try with this during your measurement tests, please?

Please let me know if you have more questions or comments.

Best regards,
Luis Fernando Rodríguez S.

Hi Luis, today I run several test on my board.

I add 10uF to IOVDD and DVDD, I don't notice any improvment

I remove a step up DC/DC that I use to change 3.7V to 5V. I supply my board directly with 5V power supply. I don't notice any improvment

I put low pass filter on the HP output. I don't notice any improvment

This is a picture of my board:

This is an image of my oscilloscope measuring the HP output before the LP filter.

You can see that I have several armonics with a difference of 50dB from the fundamental frecuency.

The sound is driven by a miniature loudspeaker on an otoacustic probe. In the same probe we have a microphone. We use that microphone to read the signal emited by the speacker. We amplify that signal and put it back to the codec. Then I read the signal on my microcontroller and send to my PC. Then I use matlab to analize the signal looking for harmonics.

This is a graph of THD analysis:

Could I replicate THD measurement using TLV320AIC3110EVM-U board? If yes, please tell me how to proceed.

Thank

BTW here you can see output signal and FFT analisys on HP output without Attenuation:

In previouse post I have -30dB attenuation on the HP ouptut.

BR

Hi, Diego,

Thank you for provide this information. This is helpful to understand the actual issue.

Could you provide your registers configuration to have a better approach to this issue? Specially, I would like to verify the clocks settings. Could you provide the MCLK, WCLK and BCLK frequency values?

The TLV320AIC3110EVM-U board is really useful to verify the AIC3110 behavior. You may use it to verify how the device should work. Do you have one of these boards? You may request one of these boards on ti.com: www.ti.com/.../tlv320aic3110evm-u

Best regards,
Luis Fernando Rodríguez S.

Hi, Luis, we try several configurations.

The source of the clock's signal is a 12MHz crystal. It is connected to my stm32f4 uC. It has a dedicated I2S PLL. So, configuring some register I have MCLK as an output of my uC. The same for BCLK and WCLK. When I want to work at Fs=44100Hz then I config I2S PLL to output 135.5MHz and the I2S hardware divide it to obtain diferent signals.
The real WS output frecuency for Fs=44100 is 44108.07422

Bit clock is 2 * 32 * WS = 2822916,75008 Hz

MCLK is 256 x WS = 11291667,00032 Hz

Then, I configure the codec with this pice of code:

void Codec_Init(void)
{
	// Reset the Codec by pulling down RESET pin for 10ns
	HAL_GPIO_WritePin(GPIOA, TLV_RESET_Pin, GPIO_PIN_RESET);
	HAL_Delay(1);		//1 mseg for test
	HAL_GPIO_WritePin(GPIOA, TLV_RESET_Pin, GPIO_PIN_SET);

	//See page 64 datasheet
	Codec_PageSelect(0);
	Codec_Reset();		// Software reset
	HAL_Delay(1);

	/* CODEC_CLKIN = MCLK = 11.289.600 Hz
	 * DAC_CLK = CODEC_CLKIN / NDAC = 11.289.600 / 1 = 11.289.600
	 * DAC_MOD_CLK = DAC_CLK / MDAC = 22.579.200 / 2 = 5.644.800
	 * DAC_fs = DAC_MOD_CLK/DOSR = 5.644.800/128 = 44.100
	 */
	Codec_RegWrite(CODEC_REG_DAC_NDAC, 0x81);		//DAC NDAC_VAL is powered up and set to 2
	Codec_RegWrite(CODEC_REG_DAC_MDAC, 0x82);		//DAC MDAC_VAL is powered up and set to 2

	Codec_RegWrite(CODEC_REG_DAC_DOSR_MSB, 0x00); 	//DAC_DOSR_MSB -> 00
	Codec_RegWrite(CODEC_REG_DAC_DOSR_LSB, 0x80); 	//DAC_DOSR_LSB -> 80  -> DOSR = 128

	Codec_RegWrite(CODEC_REG_ADC_NADC, 0x81);		//ADC NADC is powered up and set to 4
	Codec_RegWrite(CODEC_REG_ADC_MADC, 0x82);		//ADC MADC is powered up and set to 4

	Codec_RegWrite(CODEC_REG_ADC_AOSR, 0x80);		//ADC AOSR_VAL 00-> 128

    Codec_RegWrite(CODEC_REG_IF_CTRL, CODEC_I2S_WORD_LEN_24);      // I2S, 24bits

	Codec_PageSelect(0);
	//MIC
	Codec_RegWrite(CODEC_REG_ADC_DIGMIC, 0x82);			// ADC channel is power up, ADC chan vol ctrl soft steping disable
	Codec_RegWrite(CODEC_REG_ADC_DIGVOL, 0x00);			//ADC channel not mute, ADC 0 dB volume
	//SPEAK
	Codec_RegWrite(CODEC_REG_DAC_PATH, 0b11010110);		// Left and Right channel DAC power up. L ch to L data, R ch to R data. Soft Step Disabled
	Codec_RegWrite(CODEC_REG_DAC_VOL, 0x00);			// unmute DAC channels, independent volume

	Codec_PageSelect(1);
	//SPEAK
	Codec_RegWrite(CODEC_REG_HP, 0b11010100);			// HPL/R PowerUp. Output CM 1.65V
	Codec_RegWrite(CODEC_REG_OUTPUT_MIXER, 0b01000100);	// DAC_L and DAC_R to X-CH Mixer Amplifier
	Codec_RegWrite(CODEC_REG_HPL_VOL, 0x80);			// Un-mute and 0dB on HP - table 5-38 on pg 62
	Codec_RegWrite(CODEC_REG_HPR_VOL, 0x80);			// Un-mute and 0dB on HP - table 5-38 on pg 62
	Codec_RegWrite(CODEC_REG_HPL_DRIVER, 0b00000110);	// HPL PGA=0dB, HPL un-mute
	Codec_RegWrite(CODEC_REG_HPR_DRIVER, 0b00000110);	// HPR PGA=0dB, HPR un-mute

	//MIC
	//MICBIAS 0x09-> 2V, 0x0A->2.5V
	Codec_RegWrite(CODEC_REG_MICBIAS, 0x09);
	Codec_RegWrite(CODEC_REG_MICPGA, 0x80);					// MIC PGA -> 0dB
	Codec_RegWrite(CODEC_REG_ADC_FINEGAIN, 0b00100000);		// MIC1RP and 20Kohm. pg 107
	Codec_RegWrite(CODEC_REG_ADC_INP_M, 0x00);				// CM and MIC1LM are not selected for mic PGA
}

I print some oscilloscope image for more reference:

WS and BCLK

More details for those signals

MCLK and BCLK

More details on MCLK:

Just to get in maind what we are talking about, FFT of the HP Output with the pass filter installed.

you can see (I hope) a noise floor of -80dB and the harmonics with -60dB from the fundamental.

I'm the software/digital part of the project. My partner is working on the analog part of the project and he want to know what kind  (Part number will be fantastic) of LDO should he use for IOVDD, HPVDD and AVDD. Should they do 3 different LDO?

We use a LiIon 3.7V battery, then we convert that voltage to 5V (to power another part of the project) using a TPS61230. From that 5V rail we get voltage for one 3.3V and one 1.8 LDO to power the uC and digital/analog part of the CODEC. Our LDO's are TPS73233 and TPS73218.

Remeber, we invest 2 year on this project and we really need to get the performance that the DS state. So, please, let me know how can I improve the performance of the codec. We thoug that the performance on DS will be easy to achive and now that we are measuring THD we see that it is not so easy.

I have TLV320AIC3110EVM-U do you think tha we can get the performance stated on the DS with this board?

Thank and best regards

Hi, Diego,

There are several root causes that may be involved with this issue.

We always suggest to have an exact sample rate in order to get an expected result. You mentioned that the clock settings are being generated externally. Is there a way to get an exact WCLK and BCLK values with your external PLL?

Then, our TLV320AIC3110EVM-U can get the stated performance. You may try with the typical configurations of the CodecControl Software. I recommend to try with the Playback example configuration.

Regarding your question about the power supplies, HPVDD and AVDD can be connected to the same power supply. You may use the TPS73233-EP to get voltage of 3.3V. IOVDD is a digital power pin, so this should be tied to a different supply. It can be TPS73233-EP in case of 3.3V is required or TPS73218-EP if 1.8V is required.

Best regards,
Luis Fernando Rodríguez S.

Currently codec clock in is MCKL output from my uC. To get exactly 48.000Hz on WS I have to turnf of MCLK signal. If I do that then I have to drive CODEC with BCLK signal. This signal is 32*2*Fs = 3.072.000 Hz. Do the codec work properly with this CODEC CLK IN frecuency? I can config NDAC = 1, MDAC = 1 and DOSR to 64. But decimation filter A stated DOSR=128 for best performance. I could turn on the CODEC PLL but DS indicate that THD=-86dB is measured with PLL of

Should I try this setup with or without PLL on?

I have a gw instek sfg-2110 but it has -55dBc. How can I get a sin wave with -90dBc?

you want that I put a perfect sinwave on MIC input and measure THD on HP ouptut, right?

could I made similar test but using I2S interface? Could I create a digital sine wave with my uC and connect it to EVM and measure THD on HP output?

I want to isolate the problem. It could be from digital (I2S, Clocks, etc) or it could be from Power Supply and layout issue, right? Could I use internal digital sine generator to isolate the problem? If I measure THD using internal DSW generator then the problem should be from PS or layout problem, right?

Best regards

Hi, Diego,

3.072MHz is ideal for 32-bit and two channels application. If you are looking to use DOSR = 128 (which would be the best), you may use the BCLK as 1.536MHz for a 16-bits word length. We recommend not to use the PLL since it would require more power consumption.

Actually, the headphone THD tests are made just in playback mode. I mean, you should be able to send a digital sine wave signal to the DAC. Then, route the DAC output to the headphone output. Do you have better results with this test?

Best regards,
Luis Fernando Rodríguez S.