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TLV320DAC3100: How to run TLV320DAC3100 over a 16:1 sample rate ratio without changing any registers.

David Harrison
Intellectual 480 points
Part Number: TLV320DAC3100

Hello, I have an unusual application where I am generating artificial Doppler shift from a TLV320DAC3100. Nominal sample rate, with no Doppler shift, is 44100 samples/second. But I want to dynamically on-the-fly change the playback sample rate by up to four times faster and four times slower, so up to around 180000 and down to 11025 samples/second. I want to configure the TLV320DAC3100 as an I2S master and supply it with a single master MCLK and have it generate the appropriate BITCLK and LRCLKs to feed into the system microcontroller which plays back the sound file from an SD card.

The master MCLK comes from an external fractional-n-synthesizer chip (Silicon Labs SI5351) whose output is then varied over the 16:1 frequency range

Can the TLV320DAC3100 work in that mode?

I am concerned because, in its datasheet, in section 7.3.10.14 DAC Setup, it states :

"In all cases, DOSR is limited in its range by the following condition: 2.8 MHz < DOSR × DAC_fS < 6.2 MHz"

That frequency range is only a little over 2:1, nowhere near my required 16:1 range, unless I also mess with the DOSR register value.

What is the reason for that frequency range limitation?,  and can the TLV320DAC3100 be configured to operate over a 16:1 range of input MLCK and still work correctly without changing any register settings?


Another question. Could the TLV320DAC3100's own internal PLL be configured to provide the required BITCLK and LRLCKs from a fixed MCLK input by changing it's PLL fractional-n ratio on-the-fly whilst the DAC is playing back? Or can those PLL registers only be changed in a static non-playback state?

Thanks.

  • 0
    TI__Guru* 84915 points
    Hi, David,

    Regarding your question about the DOSR condition, it only applies to the sampling frequencies 44.1KHz and 48KHz.

    The PLL and dividers values can be modified in order to generate a different BCLK and WCLK. However, we don't recommend to modify the sampling rate on-the-fly. You should disable the DAC blocks before any change on the PLL and dividers. Otherwise, there could be a wrong sampled signal even if the PLL and dividers conditions are respected.

    Best regards,
    Luis Fernando Rodríguez S.
  • 0 in reply to Luis Fernando Rodriguez S.
    Intellectual 480 points

    Luis, thanks for that. Obviously for my application I cannot stop the DAC while I make DAC register changes, as the playback must be continuous whilst the playback rate changes (adding artificial Doppler shift).

    So I will try both methods, i.e. using an external variable frequency clock generator chip and leaving all the TLV3320DAC3100 registers fixed, and having a fixed frequency input to the DAC and changing its PLL registers on-the fly. OK, so we might miss a sample or two but this is not a hi-fidelity application so it probably wouldn't be noticed. That is the preferable solution to me as this is a very cost sensitive consumer application and I could save $2 or so on the external clock generator chip.


    I'll post here after my testing to let you know how I get on.