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TLV320AIC3268: IN2L/IN2R to ASI#2

Durka88
Prodigy 140 points
Part Number: TLV320AIC3268

Hello, I'm trying to follow the example script #6.1 to use the IN2L/IN2R on the TLV320AIC3268EVM as an input and have the output be ASI#2 (with the specifications below). I've gotten this same ASI#2 configuration to work before but that was when I was sending digital audio to the TLV320AIC3268EVM (see link below). So i know the A2S configurations work. However, what I'm not sure is how to route the IN2L/R correctly. Am I missing anything with my configurations? 

https://e2e.ti.com/support/data_converters/audio_converters/f/64/p/613747/2262891#2262891

I2S Specifications:

  • Using ASI#2 , BCLK2, WCLK2, DIN2, DOUT2
  • BCLK2 to be used as the DAC_CLKIN
  • TLV320AIC3268 is the I2S Slave
  • Left justified
  • MSB of SD data occurs in the second SCLK period
  • When WS is high, SD data is right channel
  • 17-bit data is rounded down to 16-data.
  • Sample Frequency 44.1kHz
  • 32 bit

#########################################################################################
# Input from IN2L/IN2R to Audio Serial Interface #2
# LOL and LOR are mixed 0dB/0dB to convert stereo to mono
# AVDDx_18, HVDD_18, CPVDD_18 = 1.8V; IOVDDx_33, RECVDD_33 = 3.3V
# SVDD, MICBIAS_VDD (JP37 1-2 + JP44 2-3), SPK_V = 5V, DVdd_18 = 1.8V
# No Master Clock, BLKC2 to be used as CLKIN
# MCLK = NA, BCLK2 = DAC_CLKIN = 1.4112MHz, Fs = 44.1kHz
# PLL Disabled, DOSR = 32,
# Audio Serial Interface #2 signals routed to DIN2 (DIN), BCLK2 (BCLK), DOUT2 (DOUT),
# WCLK2 (WCLK) - Codec ASI#2 is Slave
#########################################################################################

#########################################################################################
# Codec Software Reset
#########################################################################################
w 30 00 00 # Initialize to Page 0
w 30 7f 00 # Initialize to Book 0
w 30 01 01 # Initialize the device through software reset
d 1        # Delay 1 millisecond

#########################################################################################
# FIFO Configuration
#########################################################################################
w 30 00 00 # Select Page 0
w 30 7f 78 # Select Book 120
w 30 32 80 # Enable DAC FIFO
w 30 7f 64 # Select Book 100
w 30 32 80 # Enable ADC FIFO
w 30 7f 00 # Select Book 0

#########################################################################################
# Power and Analog Configuration
#########################################################################################
w 30 00 04 # Select Page 4
w 30 77 c0 # Disable miniDSP power-up sync with ASI
w 30 00 00 # Select Page 0
w 30 0d 00 10 # Program DOSR = 16 -AB
w 30 14 10 # Program AOSR = 16 -AB
w 30 00 01 # Select Page 1
w 30 01 00 # Disable weak AVDD to DVDD connection, make analog supplies available

#########################################################################################
# For BiQuad Configuration see Script '0.1.txt'
#########################################################################################

b "Device Initialized and in Standby"

#########################################################################################
# Clock configuration
# MCLK = NA, WCLK = 44.1 kHz (slave)
# BCLK = 44.1kHz * 32bit * 1 channel = 1.4112 MHz
#########################################################################################
w 30 00 00 # Select Page 0
w 30 04 40 # Set DAC_CLKIN as BCLK -AB
w 30 0b 81 # NDAC = 1
w 30 0c 82 # MDAC = 2
#BCLK = 44.1kHz * 32bit * 1 channel = 1.4112 MHz
w 30 0d 00 # Program the OSR of DAC to 16 to get 
w 30 0e 10 # DAC_FS = DAC_MOD_CLK / DOSR = 1.4112MHz / 32 = 44.1kHz  -AB

#########################################################################################
# Audio Serial Interface Routing Configuration - Audio Serial Interface #2
# ASI #2 connected to BCLK2, WCLK2, DIN2, and DOUT2 pins
#########################################################################################
w 30 00 04 # Select Page 4
w 30 11 18 # Audio Serial Interface #2 = I2S mode, 32-bit -AB
w 30 1a 00 # For Audio Serial Interface #1,
           # Select BCLK2 as BCLK input and WCLK2 as WCLK input
w 30 17 01 # Route ADC data to Audio Serial Interface #2
w 30 18 50 # ASI#2 Left Channel data sent to Left Channel DAC,
           # ASI#2 Right channel data sent to Right Channel DAC
w 30 45 04 # Select WCLK2 pin as WCLK for Audio Serial Interface #2
w 30 46 04 # Select BCLK2 pin as BCLK for Audio Serial Interface #2
w 30 47 22 # Select DOUT2 pin as DOUT for Audio Serial Interface #2
w 30 48 20 # Select DIN2 pin as DIN for Audio Serial Interface #2
w 30 76 16 # Only ASI#2 Routed to DAC miniDSP Data Input 1

#########################################################################################
# Signal Processing Settings
#########################################################################################
w 30 00 00 # Select Page 0
w 30 3d 01 # Set the ADC PRB Mode to PRB_R1

#########################################################################################
# ADC Input Channel Configuration --- IN2L / IN2R
#########################################################################################
w 30 00 01 # Select Page 1
w 30 08 00 # Set the input common mode to 0.9V
w 30 34 20 # Route IN2L and CM1 to LEFT ADCPGA with 20K input impedance
w 30 36 80
w 30 37 20 # Route IN2R and CM1 to RIGHT ADCPGA with 20K input impedance
w 30 39 80
w 30 3B 18 # Left Channel Analog ADC PGA = 12 dB -> Overall Channel Gain of 0dB
w 30 3C 18 # Right Channel Analog ADC PGA = 12 dB -> Overall Channel Gain of 0dB
w 30 3D 00 # ADC Analog programmed for PTM_R4
w 30 00 00 # Select Page 0
w 30 51 C0 # Power-up ADC Channel
w 30 52 00 # Unmute ADC channel and Fine Gain = 0dB
d 42       # Wait for reference power up and input coupling cap to charge 

b "Device in Operational Mode"
#########################################################################################
# For Power Down Sequence see Script '0.2.txt'
#########################################################################################

  • 0
    TI__Guru 57800 points

    Hi, Durka,

    I took a quick look to your code and it seems the ADC clocks are not correctly configured, as the code you are showing is only configuring the DAC clocks. Pleas try correcting this and let me know if there is any improvement.

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 140 points

    Thank you! I'll give that a shot. If I'm going to be sending/receiving audio is it ok to have both DAC and ADC clock configured to the same pin (BCLK2)?

    This look right?

    #########################################################################################
# Clock configuration
# MCLK = NA, WCLK = 44.1 kHz (slave)
# BCLK = 44.1kHz * 32bit * 1 channel = 1.4112 MHz
#########################################################################################
w 30 00 00 # Select Page 0
w 30 04 04 # Set ADC_CLKIN as BCLK2 -AB
w 30 12 81 # Power Up NADC, NADC = 1
w 30 13 82 # Power Up MADC, MADC = 2
                   #BCLK = 44.1kHz * 32bit * 1 channel = 1.4112 MHz
w 30 14 10 # Program the OSR of ADC to 16 to get 
                   # ADC_FS = ADC_MOD_CLK / AOSR = 1.4112MHz / 32 = 44.1kHz  -AB

  • 0 in reply to Durka88
    TI__Guru 57800 points

    Hi, Durka,

    The configuration seems correct in general. One thing to note is that BCLK is setup as 32×Fs, this value is valid only when the data size is 16-bit. 

    Best Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 140 points

    Yeah I got it to make some noise but it sounds horrible you can't hear anything but static. Why is it only valid when the data size is 16bit? Are you saying I should change everything to 16bit rather then 32 bit?

  • 0 in reply to Durka88
    Prodigy 140 points

    Any Suggestion Diego? 

    #########################################################################################
# Input from IN2L/IN2R to Audio Serial Interface #2
# LOL and LOR are mixed 0dB/0dB to convert stereo to mono
# AVDDx_18, HVDD_18, CPVDD_18 = 1.8V; IOVDDx_33, RECVDD_33 = 3.3V
# SVDD, MICBIAS_VDD (JP37 1-2 + JP44 2-3), SPK_V = 5V, DVdd_18 = 1.8V
# No Master Clock, BLKC2 to be used as CLKIN
# MCLK = NA, BCLK2 = DAC_CLKIN = 1.4112MHz, Fs = 44.1kHz
# PLL Disabled, AOSR = 16,
# Audio Serial Interface #2 signals routed to DIN2 (DIN), BCLK2 (BCLK), DOUT2 (DOUT),
# WCLK2 (WCLK) - Codec ASI#2 is Slave
#########################################################################################

#########################################################################################
# Codec Software Reset
#########################################################################################
w 30 00 00 # Initialize to Page 0
w 30 7f 00 # Initialize to Book 0
w 30 01 01 # Initialize the device through software reset
d 1        # Delay 1 millisecond

#########################################################################################
# FIFO Configuration
#########################################################################################
w 30 00 00 # Select Page 0
w 30 7f 78 # Select Book 120
w 30 32 80 # Enable DAC FIFO
w 30 7f 64 # Select Book 100
w 30 32 80 # Enable ADC FIFO
w 30 7f 00 # Select Book 0

#########################################################################################
# Power and Analog Configuration
#########################################################################################
w 30 00 04 # Select Page 4
w 30 77 c0 # Disable miniDSP power-up sync with ASI
w 30 00 00 # Select Page 0
w 30 0d 00 10 # Program DOSR = 16 -AB
w 30 14 10 # Program AOSR = 16 -AB
w 30 00 01 # Select Page 1
w 30 01 00 # Disable weak AVDD to DVDD connection, make analog supplies available

#########################################################################################
# For BiQuad Configuration see Script '0.1.txt'
#########################################################################################

b "Device Initialized and in Standby"

#########################################################################################
# Clock configuration
# MCLK = NA, WCLK = 44.1 kHz (slave)
# BCLK = 44.1kHz * 16bit * 2 channel = 1.4112 MHz
#########################################################################################
w 30 00 00 # Select Page 0
w 30 04 04 # Set ADC_CLKIN as BCLK2 -AB
w 30 12 81 # Power Up NADC, NADC = 1
w 30 13 82 # Power Up MADC, MADC = 2
                   #BCLK = 44.1kHz * 16bit * 2 channel = 1.4112 MHz
w 30 14 10 # Program the OSR of ADC to 16 to get 
                   # ADC_FS = ADC_MOD_CLK / AOSR = 1.4112MHz / 32 = 44.1kHz  -AB

#########################################################################################
# Audio Serial Interface Routing Configuration - Audio Serial Interface #2
# ASI #2 connected to BCLK2, WCLK2, DIN2, and DOUT2 pins
#########################################################################################
w 30 00 04 # Select Page 4
w 30 11 00 # Audio Serial Interface #2 = I2S mode, 16-bit -AB
w 30 1a 00 # For Audio Serial Interface #1,
           # Select BCLK2 as BCLK input and WCLK2 as WCLK input
w 30 17 01 # Route ADC data to Audio Serial Interface #2
w 30 18 50 # ASI#2 Left Channel data sent to Left Channel DAC,
           # ASI#2 Right channel data sent to Right Channel DAC
w 30 45 04 # Select WCLK2 pin as WCLK for Audio Serial Interface #2
w 30 46 04 # Select BCLK2 pin as BCLK for Audio Serial Interface #2
w 30 47 22 # Select DOUT2 pin as DOUT for Audio Serial Interface #2
w 30 48 20 # Select DIN2 pin as DIN for Audio Serial Interface #2
w 30 76 16 # Only ASI#2 Routed to DAC miniDSP Data Input 1

#########################################################################################
# Signal Processing Settings
#########################################################################################
w 30 00 00 # Select Page 0
w 30 3d 01 # Set the ADC PRB Mode to PRB_R1

#########################################################################################
# ADC Input Channel Configuration --- IN2L / IN2R
#########################################################################################
w 30 00 01 # Select Page 1
w 30 08 00 # Set the input common mode to 0.9V
w 30 34 20 # Route IN2L and CM1 to LEFT ADCPGA with 20K input impedance
w 30 36 80
w 30 37 20 # Route IN2R and CM1 to RIGHT ADCPGA with 20K input impedance
w 30 39 80
w 30 3B 18 # Left Channel Analog ADC PGA = 12 dB -> Overall Channel Gain of 0dB
w 30 3C 18 # Right Channel Analog ADC PGA = 12 dB -> Overall Channel Gain of 0dB
w 30 3D 00 # ADC Analog programmed for PTM_R4
w 30 00 00 # Select Page 0
w 30 51 C0 # Power-up ADC Channel
w 30 52 00 # Unmute ADC channel and Fine Gain = 0dB
d 42       # Wait for reference power up and input coupling cap to charge 

b "Device in Operational Mode"
#########################################################################################
# For Power Down Sequence see Script '0.2.txt'
#########################################################################################

  • 0 in reply to Durka88
    TI__Guru 57800 points

    Hi, Durka,

    After detailed revision,  the issue is related with the clock configuration. I found that the problem is that AOSR is setup as 16, when using PRB_R1, AOSR should be either 64 or 128. The BCLK frequency used in your system is quite low to be directly used as the system clock source, so I would recommend you to configure the PLL to generate a higher clock from BCLK2 source.  

    Regards,

      -Diego Meléndez López
       Audio Applications Engineer

  • 0 in reply to Diego Melendez
    Prodigy 140 points

    What is a valid range for the BLCK2 then? I changed it to 32bit to get 2.8224MHz  and the AOSR to 64 but still have nothing but static. Also, why does it have to be 64 or 128? 

    #########################################################################################
# Input from IN2L/IN2R to Audio Serial Interface #2
# LOL and LOR are mixed 0dB/0dB to convert stereo to mono
# AVDDx_18, HVDD_18, CPVDD_18 = 1.8V; IOVDDx_33, RECVDD_33 = 3.3V
# SVDD, MICBIAS_VDD (JP37 1-2 + JP44 2-3), SPK_V = 5V, DVdd_18 = 1.8V
# No Master Clock, BLKC2 to be used as CLKIN
# MCLK = NA, BCLK2 = DAC_CLKIN = 2.8224MHz,Fs = 44.1kHz
# PLL Disabled, DOSR = 32,
# Audio Serial Interface #2 signals routed to DIN2 (DIN), BCLK2 (BCLK), DOUT2 (DOUT),
# WCLK2 (WCLK) - Codec ASI#2 is Slave
#########################################################################################

#########################################################################################
# Codec Software Reset
#########################################################################################
w 30 00 00 # Initialize to Page 0
w 30 7f 00 # Initialize to Book 0
w 30 01 01 # Initialize the device through software reset
d 1        # Delay 1 millisecond

#########################################################################################
# FIFO Configuration
#########################################################################################
w 30 00 00 # Select Page 0
w 30 7f 78 # Select Book 120
w 30 32 80 # Enable DAC FIFO
w 30 7f 64 # Select Book 100
w 30 32 80 # Enable ADC FIFO
w 30 7f 00 # Select Book 0

#########################################################################################
# Power and Analog Configuration
#########################################################################################
w 30 00 04 # Select Page 4
w 30 77 c0 # Disable miniDSP power-up sync with ASI
w 30 00 00 # Select Page 0
w 30 0d 00 40 # Program DOSR = 64 -AB
w 30 14 40 # Program AOSR = 64 -AB
w 30 00 01 # Select Page 1
w 30 01 00 # Disable weak AVDD to DVDD connection, make analog supplies available

#########################################################################################
# For BiQuad Configuration see Script '0.1.txt'
#########################################################################################

b "Device Initialized and in Standby"

#########################################################################################
# Clock configuration
# MCLK = NA, WCLK = 44.1 kHz (slave)
# BCLK = 44.1kHz * 32bit * 2 channel = 2.8224 MHz
#########################################################################################
w 30 00 00 # Select Page 0
w 30 04 04 # Set ADC_CLKIN as BCLK2 -AB
w 30 12 81 # Power Up NADC, NADC = 1
w 30 13 81 # Power Up MADC, MADC = 1
                   #BCLK = 44.1kHz * 32bit * 2 channel = 2.8224 MHz
w 30 14 40 # Program the OSR of ADC to 64 to get 
                   # ADC_FS = ADC_CLKIN / (NADC * MADC * AOSR) = 2.8224/ (1*1*64) = 44.1kHz  -AB

#########################################################################################
# Audio Serial Interface Routing Configuration - Audio Serial Interface #2
# ASI #2 connected to BCLK2, WCLK2, DIN2, and DOUT2 pins
#########################################################################################
w 30 00 04 # Select Page 4
w 30 11 18 # Audio Serial Interface #2 = I2S mode, 32-bit -AB
w 30 1a 00 # For Audio Serial Interface #1,
           # Select BCLK2 as BCLK input and WCLK2 as WCLK input
w 30 17 01 # Route ADC data to Audio Serial Interface #2
w 30 18 50 # ASI#2 Left Channel data sent to Left Channel DAC,
           # ASI#2 Right channel data sent to Right Channel DAC
w 30 45 04 # Select WCLK2 pin as WCLK for Audio Serial Interface #2
w 30 46 04 # Select BCLK2 pin as BCLK for Audio Serial Interface #2
w 30 47 22 # Select DOUT2 pin as DOUT for Audio Serial Interface #2
w 30 48 20 # Select DIN2 pin as DIN for Audio Serial Interface #2
w 30 76 16 # Only ASI#2 Routed to DAC miniDSP Data Input 1

#########################################################################################
# Signal Processing Settings
#########################################################################################
w 30 00 00 # Select Page 0
w 30 3d 01 # Set the ADC PRB Mode to PRB_R1

#########################################################################################
# ADC Input Channel Configuration --- IN2L / IN2R
#########################################################################################
w 30 00 01 # Select Page 1
w 30 08 00 # Set the input common mode to 0.9V
w 30 34 20 # Route IN2L and CM1 to LEFT ADCPGA with 20K input impedance
w 30 36 80
w 30 37 20 # Route IN2R and CM1 to RIGHT ADCPGA with 20K input impedance
w 30 39 80
w 30 3B 18 # Left Channel Analog ADC PGA = 12 dB -> Overall Channel Gain of 0dB
w 30 3C 18 # Right Channel Analog ADC PGA = 12 dB -> Overall Channel Gain of 0dB
w 30 3D 00 # ADC Analog programmed for PTM_R4
w 30 00 00 # Select Page 0
w 30 51 C0 # Power-up ADC Channel
w 30 52 00 # Unmute ADC channel and Fine Gain = 0dB
d 42       # Wait for reference power up and input coupling cap to charge 

b "Device in Operational Mode"
#########################################################################################
# For Power Down Sequence see Script '0.2.txt'
#########################################################################################