TLV320AIC3100: AIC3100 vs. DAC3100 init

Ahmad Alsaleem

Prodigy 230 points

Part Number: TLV320AIC3100
Other Parts Discussed in Thread: TLV320DAC3100

I used the DAC3100 in one design.

I replaced with AIC3100 as I needed the input functionality.

However, when I run the init code for DAC3100 in AIC3100's, I got no output.

The registers look the same, Is there anything else I should add to init. Now I am using only DAC functionality.

Note: I am using my embedded design.

Thanks.

over 5 years ago

0 Steve-Wilson over 5 years ago

TI__Mastermind 30030 points

Ahmad,

Can you provide your register configuration?

best regards,
-Steve Wilson

0 Ahmad Alsaleem over 5 years ago in reply to Steve-Wilson

Prodigy 230 points

aic3100-init.txt

audio-reset v1.4
do codec reset
I2C 18 00 00
I2C 18 01 01
do codec PLL
I2C 18 04 07
I2C 18 06 08
I2C 18 07 00
I2C 18 08 00
I2C 18 05 98
I2C 18 0B 82
I2C 18 0C 88
I2C 18 12 01
I2C 18 13 01
I2C 18 0D 00
I2C 18 0E 80
I2C 18 14 80
do codec iface
I2C 18 1B 00
I2C 18 1C 00
I2C 18 1D 00
do codec dac/spkr
I2C 18 3C 19
I2C 18 00 08
I2C 18 01 04
I2C 18 00 00
I2C 18 74 00
I2C 18 00 01
I2C 18 1F 04
I2C 18 21 4E
I2C 18 23 44
I2C 18 28 06
I2C 18 29 06
I2C 18 2A 1C
I2C 18 1F C2
I2C 18 20 86
I2C 18 24 86
I2C 18 25 86
I2C 18 26 92
I2C 18 00 00
I2C 18 3F D4
I2C 18 41 F8
I2C 18 42 F8
I2C 18 40 00
do codec adc/mic
I2C 18 00 01
I2C 18 2E 0A
I2C 18 2F 80
I2C 18 30 80
I2C 18 31 80
I2C 18 00 00
I2C 18 51 80
I2C 18 52 00
I2C 18 53 00
audio cfg OK

here is my config sequence. I have included the ADC config seq. (& commented)

constants were taken from the linux driver header file. (tlv320aic31xx.h). Raw binary is also attached.

const struct aic3100_reg aic31xx_init[] = {
	{ AIC31XX_PAGECTL		, 0x00 }, // set page 0
	{ AIC31XX_RESET			, 0x01 }, // soft reset
// PLL
	{ AIC31XX_CLKMUX		, 0x07 }, // PLL_clkin = BCLK,codec_clkin = PLL_CLK
	{ AIC31XX_PLLJ			, 0x08 }, // PLL J=8
	{ AIC31XX_PLLDMSB		, 0x00 }, // PLL D = 0
	{ AIC31XX_PLLDLSB		, 0x00 },
	{ AIC31XX_PLLPR			, 0x98 }, // PLL Power up, P = 1, R = 8
	{ AIC31XX_NDAC			, 0x82 }, // NDAC is powered up and set to 2
	{ AIC31XX_MDAC			, 0x88 }, // MDAC is powered up and set to 8
	//{ AIC31XX_NADC		, 0x01 }, // default, take from DAC
	//{ AIC31XX_MADC		, 0x01 }, // default, take from DAC
	{ AIC31XX_DOSRMSB		, 0x00 }, // DOSR = 128, DOSR(9:8) = 0, DOSR(7:0) = 128
	{ AIC31XX_DOSRLSB		, 0x80 }, //
	//{ AIC31XX_AOSR		, 0x80 }, // AOSR = 128
// interface
	{ AIC31XX_IFACE1		, 0x00 }, // mode is i2s, wordlength is 16, slave mode
	{ AIC31XX_DATA_OFFSET	, 0x00 }, // BCLK delay after WCLK rising edge = 0
	{ AIC31XX_IFACE2		, 0x00 }, // BCLK is not inverted
// DAC
	{ AIC31XX_DACPRB		, 0x19 }, // Select Processing Block PRB_P25
	{ AIC31XX_PAGECTL		, 0x08 }, // set page 8
	{ AIC31XX_DAC_COEF		, 0x04 }, // Adaptive filtering enabled in DAC processing block
	{ AIC31XX_PAGECTL		, 0x00 }, // set page 0

	{ AIC31XX_DAC_VOLCTRL	, 0x00 }, // DAC => volume control thru pin disable
	{ AIC31XX_PAGECTL		, 0x01 }, // set page 1
	{ AIC31XX_HPDRIVER		, 0x04 }, // Program common-mode voltage (defalut = 1.35 V)
	{ AIC31XX_HPPOP			, 0x4E }, // De-pop, Power on = 800 ms, Step time = 4 ms
	{ AIC31XX_DACMIXERROUTE	, 0x44 }, // LDAC routed to HPL out, RDAC routed to HPR out
	{ AIC31XX_HPLGAIN		, 0x06 }, // Unmute HPL, set gain = 0 db
	{ AIC31XX_HPRGAIN		, 0x06 }, // Unmute HPR, set gain = 0 db
	{ AIC31XX_SPLGAIN		, 0x1c }, // Unmute Class-D, xx=gain = (6/12/18/24 dB) 6 dB <== ? hot speaker on 18dB+ (000xxM00) (M=muted)
	{ AIC31XX_HPDRIVER		, 0xC2 }, // HPL and HPR powered up
	{ AIC31XX_SPKAMP		, 0x86 }, // Power-up Class-D driver
	{ AIC31XX_LANALOGHPL	, 0x86 }, // Enable HPL output analog volume, set = -9 dB
	{ AIC31XX_RANALOGHPR	, 0x86 }, // Enable HPR output analog volume, set = -9 dB
	{ AIC31XX_LANALOGSPL	, 0x92 }, // Enable Class-D output analog volume, set = -9 dB
	{ AIC31XX_PAGECTL		, 0x00 }, // set page 0
	{ AIC31XX_DACSETUP		, 0xD4 }, // Powerup DAC left and right channels (soft step enabled)
	{ AIC31XX_LDACVOL		, 0xF8 }, // DAC Left gain = -3 dB
	{ AIC31XX_RDACVOL		, 0xF8 }, // DAC Right gain = -3 dB
	{ AIC31XX_DACMUTE		, 0x00 }, // Unmute DAC left and right channels
// mic /ADC
	//{ AIC31XX_PAGECTL		, 0x01 }, // set page 1
	//{ AIC31XX_MICBIAS		, 0x0A }, // MICBIAS power 2.0V, mic detect is ignored
	//{ AIC31XX_MICPGA		, 0x80 }, // mic PGA 0dB
	//{ AIC31XX_MICPGAPI	, 0x80 }, // MIC1LP is selected 10KOhm
	//{ AIC31XX_MICPGAMI	, 0x80 }, // mic PGA 0dB

	//{ AIC31XX_PAGECTL		, 0x00 }, // set page 1
	//{ AIC31XX_ADCSETUP	, 0x80 }, // ADC enable and power up
	//{ AIC31XX_ADCFGA		, 0x00 }, // unmute ADC, 0dB
	//{ AIC31XX_ADCVOL		, 0x00 }, // 0dB

	{ AIC31XX_END_PROG		, 0x00 }, // end
};

Thanks.

0 Steve-Wilson over 5 years ago in reply to Ahmad Alsaleem

TI__Mastermind 30030 points

Ahmad,

I've looked at your setup and nothing is popping out as odd or wrong. I will continue to look at it.
This is connecting to an existing platform that you use the DAC3100 with?

What is your BCLK frequency?

best regards,
-Steve Wilson

0 Ahmad Alsaleem over 5 years ago in reply to Steve-Wilson

Prodigy 230 points

my BCLK is 352.8K (11025). I am not applying MCLK but it works in DAC3100.

I can see DOUT change when I speak into the mic. (when applying the ADC configs above).

0 Ahmad Alsaleem over 5 years ago in reply to Ahmad Alsaleem

Prodigy 230 points

I can also see audio on HPR, but I am not using it. I am using the class D amp. I do not see the PWM (300K) on speaker out.
Will the Class D operate on low audio signal (from digital input)?

Could it be the speaker initialization sequence?

0 Ahmad Alsaleem over 5 years ago in reply to Ahmad Alsaleem

Prodigy 230 points

Steve,
Could you show an example of initializing the class-D driver,
- fed from MIX_L.
- gain 6-dB
- Analog Attenuation 0-dB
- switched on.

I am concerned with the init sequence because I do not see an output.
MIX_L is also being fed to HP and I can see output.

Thanks.

0 Steve-Wilson over 5 years ago in reply to Ahmad Alsaleem

TI__Mastermind 30030 points

Ahmad,

Are you sure your configuration works on the TLV320DAC3100?

1: If your BCLK is 352.8k, and your bclk is the PLL_CLKIN, You are violating the first PLL constriant for PLL_CLKIN see constraints below

2: With J=-8 and R=8 you are also violating the second constraint , You would have a 352,800*8*8/1 = 22.579MHz. This is also outside the PLL spec.

from Pg 67 of The Datasheet:

These constraints are also present for the TLV320DAC3100.

best regards,

-STeve Wilson

0 Ahmad Alsaleem over 5 years ago in reply to Steve-Wilson

Prodigy 230 points

Steve,

I see the constraint above. However and fortunately, It works. It's been several months and it is playing on DAC3100.

Actually we were planning on 22050, but switched to 11025 to reduce memory.

I can see now an audio output on HPR but not on Speaker. Does the setting for PLL prevent output on speaker?

Thanks.

0 Steve-Wilson over 5 years ago in reply to Ahmad Alsaleem

TI__Mastermind 30030 points

Ahmad,

While it may work, I would advise that you modify the PLL settings to at least meet that second constraint. This is very easy to do just change the J value to 32 and the NDAC to 4 and Mdac to 16.

regarding the speaker. if your headphones work and these registers are set as you have them the Class D amplifier should work.

AIC31XX_DACMIXERROUTE , 0x44
AIC31XX_SPKAMP , 0x86
AIC31XX_SPLGAIN , 0x1c
AIC31XX_SPLGAIN , 0x1c

I have confirmed this on an EVM.

-Steve Wilson

0 Ahmad Alsaleem over 5 years ago in reply to Steve-Wilson

Prodigy 230 points

Hi Steve,

Thanks, it works now on speaker.

I will revise the P R J registers and give feedback on the result.

It seems that these constraints are hard to obtain for low Fs (< 22050). I was even planning to use 8Ksps for VOIP application.

I am trying to avoid using external oscillator. Can this be done in these cases?

Regards,

0 Steve-Wilson over 5 years ago in reply to Ahmad Alsaleem

TI__Mastermind 30030 points

Ahmad,

The constraints for the PLL can be hard to meet when using the BCLK for low Fs.

you could change the word length to 32 or 24Bit, or use a TDM mode, where bclk= 256*Fs. Even at 8k that gives a bclk of 2.048Mhz. You wouldn’t need to use all of the channels.

best regards,

-Steve Wilson

Audio

Audio forum

TLV320AIC3100: AIC3100 vs. DAC3100 init