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Part Number: ADC12DJ3200EVM
My customer test the ADC12DJ3200EVM, they measured the noise power density by terminating the input with 50ohm. Then got results like -80dBFs/4.5MHz i.e -147.1dBFs/Hz. But as per Data Sheet -151.8dBFs/Hz should come. Can what could be the reason for this 4dB Delta?
Waiting for your reply
Attached the error screen shot.
What is the minimum sampling freq I can use in ADC GUI. Why asking this question means when I went to 800 MSPs and JMODE0 with DDC gain boost on and cal trigger running on .I am getting error while capturing the data. Similarly can you tell me minimum sampling frequency with highest decimation factor.
In reply to Star Xu:
In reply to Brian2001:
It is possible to operate with Decimate by 16 and 800 MHz clock rate, using JMODE15.
Lane rate limitations of the TSW14J57EVM capture firmware limit the minimum clock rate to higher minimum frequencies and lower maximum frequencies for specific JMODEs. The current supported lane rate range is from approximately 3.2 Gbit/sec to 12.8 Gbit/sec. The lane rate for a given JMODE and CLK frequency can be calculated using the R parameter in Table 18 in the ADC12DJ3200 datasheet.
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