ADS8860: DOUT timing to SCLK

Hello Lukas,

Welcome to the TI E2E Community.

td-CK-DO is specified to determine the setup time for the host controller. In your case, I assume your SCLK frequency is 66.6MHz, or 15nS for t-SCLK. td-CK-DO=13.4nS, which means DOUT will be valid at least (15-13.4) 1.6nS before the falling edge of SCLK. DOUT will also remain valid after the falling edge of SCLK for th-CK-DO, or 3nS min.

td-CK-DO will limit your maximum SCLK frequency if you capture data on the rising edge of SCLK. The minimum clock period in this case will be 13.4nS/0.45=30nS, or a maximum frequency of 33.3MHz.

The ADS8860 is tested with a 500uA load and 20pF of capacitance, per Figure 4 in the datasheet. The ISO7741 has a maximum input current of +/-10uA and 2pF. Parasitic board capacitance will likely double the total capacitance seen by the DOUT pin, but this is still much less than the test conditions, so you should expect to fully meet the timing specs with this load.

Regards,
Keith N.
Precision ADC Applications

Hello Keith,

Thank you for your response.

So, the td-CK-DO represents maximal setup time (limit) for correct communication with host or another ADS8860, but real setup time of DOUT will be lower. And the real setup time of DOUT is determined by application. Am I right?

Regards, Lukas.

 

Hi Lukas,

Yes, the 13.4nS value for td-CK-DO is the maximum time that you would see, provided that you meet the other operating requirements for the ADC such as supply voltage range, temperature range, loading on DOUT, etc.

If you measured this spec on a part in the lab, then the value measured would be less. However, there will be part to part differences, especially if the parts were manufactured at different times, so you need to use the maximum value when designing the system.

If I understand your question, YES, the 'real' setup time of DOUT (the value that you measure on a specific device in the lab) will depend on the specifics of the system, but it will also vary from part to part.

Regards, Keith