Question regarding using ADC12D1X00RFRB Reference Board/Wave Vision 5

I am using the ADC12D1X00RFRB reference board with Wave Vision 5 to evaluate a TI ADC.  I am able to use the internal clock with a signal generator to look at an an input signal using the Wave Vision 5 software.  According to the manual and the software options in Wave Vision 5, I am supposed to be able to input an external clock source to use with the ADC.  I have tried selecting this option and using an additional signal generator to input a clock signal and examined the output from the ADC and do not seem to be getting good results (I am using a 1.8 GHz sine wave 0 dBm per the manual July 13, 2011 rev 1.0).  Please advise on the proper way to configure the ADC12D1X00RFRB board to use an external clock source.

Thanks in advance for your time.

Mike.

  • I solved this issue.  Seems that a connector got loose

  • In reply to M P:

    Hi,

    I'm glad that you found the main issue in the setup.  In addition to that, we recommend certain specific levels at the input SMA connector for the EXT_CLK connector on the Reference Board to maintain the proper sampling clock level at the ADC.  There is a significant amount of insertion loss through the relay.  Sorry, but this information hasn't yet been updated into the Users Guide: 

    Kind regards,

    Marjorie

  • In reply to Marjorie Plisch:

    Thanks Marjorie.  What voltage levels are required for external clock frequencies below 1.0 GHz?  I am potentially interested in using an EXT_CLK of 400 MHz.  Also in the manual for the reference manual there is some discussion on using an external trigger via the EXT_TRIG SMA connector.  I seem to be following the directions listed, but do not seem to get the capture to trigger with my input signal.  I am currently using a trigger signal coming from the back of a signal generator and have set my capture mode to single capture.  Is there anything else I need to consider when trying to use this mode?

    Thanks,

    M P.

  • In reply to M P:

    5327.adc10d1000_xc4vlx25_adc12d1000rb.txtHi,

    Unfortunately, we didn't test those yet.  We were most concerned with the insertion loss at higher clock frequencies.  It is possible I could take the data, but it would not be right away.  What is your timeline?

    If you are interested in Fclk = 400MHz, consider the ADC12D800/500RF: dual channel at 800/500Msps or 1.6/1.0Gsps interleaved.  Note that only the ADC12D800RFRB is available, i.e. no ADC12D500RFRB, so use the ADC12D800RFRB to evaluate the ADC12D500RFRB.

    The ADC12D1800/6000/1000RF will work down to Fclk = 400MHz, but the Reference Board will not.  This is because the FPGA image is designed to function over a certain frequency range.  In this case, it covers 1800MHz down to 1000MHz, at least.  Depending upon the particular system, it can work down to 700MHz or so, but definitely not down to 400MHz.  The same image can be used, but it must be compiled for a lower Fclk. 

    Sorry for the difficulties regarding the trigger function.  We have added this to the FPGA image, but not yet to the released FPGA image.  Please find the FPGA image attached which will work for the trigger function and follow the below instructions to use it.

    This image has not been extensively tested, so please let us know if you run into any issues while using it.  After we test the image completely, it will be replaced as the publicly available on-line version.  One caveat; the Trigger LED is not yet implemented.

    Once the Trigger box in the GUI is enabled, the software will wait for a high signal on the Trigger Input before capturing data. If a single shot data capture has been selected, then only one data capture will be taken. If the continuous mode has been selected, then the data will continue to capture/display, as long as the signal as the Trigger Input is high.

    Here is how to swap the new image for the old one:
    1. Go to the directory:
    C:\Program Files\National Semiconductor\WaveVision5\hardware\fpga_images

    2. Find the file named "adc10d1000_xc4vlx25_adc12d1000rb.bit" and rename it to "ORIG_adc10d1000_xc4vlx25_adc12d1000rb.bit". It is important that the new name is different at the beginning, not the end, of the file name, else the old image may still be used. For example, do not name it "adc10d1000_xc4vlx25_adc12d1000rb.bit.bak"

    3. Download the attached file and save it in the fpga_images directory.  Change the extension name from "txt" to "bit".  E2E does not allow uploading files with .bit extension, so I had to change it.

     

    Kind regards,

    Marjorie

     

  • In reply to Marjorie Plisch:

    Thanks Marjorie,

    I will try to load the new FPGA firmware and let you know if there are any issues.  As far as  Fclk = 400 MHz, I have been able to use Fclk = 400 MHz using the external clock and input sinusoid of 100 MHz and the data capture appears to work with the Reference board.

     

    M P

  • In reply to M P:

    Hi,

    Sounds good.  If Fclk =400MHz is working for you, I won't spend any more time explaining why it won't!  :)  Just keep in mind that the FPGA image will function over a certain range - and this range is more restrictive than the range over which the ADC functions, as specified in the datasheet.  So, if you do see a functionality issue with an extremely low sampling clock, it's the FPGA and not the ADC.

    What are you using the trigger for?  Many customers who are interested in the trigger also find the TimeStamp feature of the ADC to be useful.  The TimeStamp feature uses the LSB to output a signal which is converted by the ADC with the exact same latency as the analog input.

     

    Kind regards,

    Marjorie

  • In reply to Marjorie Plisch:

    Marjorie,

    Haven't had a chance to test the new FPGA build, but I did some addition questions.  Is there anyway to increase the 32k limit on number of samples that the board/software can capture.  It would be nice to be able to capture larger blocks.  Second, does their exist a statement of volatility for the eval board and if so could I receive it?

    Thanks again,

    M P

  • In reply to M P:

    Unfortunately the capture size is limited by the FPGA RAM resources and cannot be increased. There are methods to capture larger amounts of data using the FMC expansion connector on the board, but those will require additional external hardware (either a logic analyzer, or a capture board compatible with the FMC connector interface). We can provide more information on those methods if you need to go that route.

    Can you provide more detail regarding the "statement of volatility" you are looking for? This is the first time I have seen the term.

    Best regards,

    Jim B

  • In reply to Jim Brinkhurst84999:

    Thanks for the response Jim.  Can you please provide more information regarding the FMC connector interface through a capture board.  I guess with the "statement of volatility" I am looking for information regarding the memory on the demo board and whether it is volatile.  Thanks, M P

  • In reply to M P:

    The FMC connector on the ADC12D1X00RFRB is compatible with the a number of different capture boards supporting the FMC standard. One such board would be the Xilinx ML-605 evaluation platform. Unfortunately we have not yet implemented a system using one of these boards, so we do not have any firmware to provide as a reference or starting point.

    The memory on the ADC12D1X00RFRB is as follows:

    Internal memory in FPGA (U5) - Volatile, FPGA is configured by the host PC via the WaveVision 5 software application.

    Internal memory in Cypress uC (U2) - Volatile. This device is configured by the host PC via the WaveVision 5 software application.

    External EEPROM (U4) connected to Cypress uC - Non-voltale. This EEPROM contains information used to identify the board so WaveVision 5 can load the appropriate uC firmware and FPGA code.

    Config Flash for FPGA (U14) - Not installed. - Non-voltatile - This is designed into the board, but we have not verified use of this device and do not have documentation to support it. If this device was to be used, the Cypress uC should be un-populated.

    Configuration register space in ADC (U1) - Volatile - This is configured by the WaveVision 5 software script via the FPGA.

    Configuration register space in PLL (U12) - Volatile - This is configured by the WaveVision 5 software script via the FPGA.

    I hope this is helpful.

    Best regards,

    Jim B