Hi,
Now our customer is evaluating and starting design their system with ADC12D500RF. Now they need to know the variation of DCLK-to-Data Output Skew (Tosk) to design the timing with FPGA. They understand that you can not guarantee it because the Tosk is not specified min/max, however they would like to know how much variation should be expected at such a high speed ADC.
Your advice will be appreciated.
Best Regards,