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High Speed Data Converters
High Speed Data Converters Forum
ADC12D500RF / DCLK-to-Data Output Skew
Now our customer is evaluating and starting design their system with ADC12D500RF. Now they need to know the variation of DCLK-to-Data Output Skew (Tosk) to design the timing with FPGA. They understand that you can not guarantee it because the Tosk is not specified min/max, however they would like to know how much variation should be expected at such a high speed ADC.
Your advice will be appreciated.
The design team has performed some Monte Carlo simulations on the skew variation due to device mismatch out to 6 sigma; (the tOSK does not vary directly for PVT variation). In addition, we padded the simulation results to include the effects of layout parasitics and process corners, and package variation. We have these recommendations:
Let us know if you have further questions.
Thank you for your response.
These information will be helpful for customer.
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