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DAC34H84

John Reyland
Prodigy 50 points
Other Parts Discussed in Thread: DAC34H84, DAC34SH84, TRF3705

Greetings support engineers,

I am considering the DAC34H84 for an application similar to a phased array antenna system.  Please verify the following operation for me:

1. DAB inputs an interleaved stream of 16 bit I and 16 bit Q complex numbers.  I and Q are clocked in on alternate edges of 1.25MHz DataClk input (as in Figure 51 of data sheet)  Thus the data rate of I is 625MHz and Q is 625 MHz.  The complex baseband signal I am inputing has a BW in the range [-312.5 +312.5] MHz. 

2. DCD is an independent complex signal with exactly the same BW and data rate as DAB

3. I enable 2X upsampler to get two separate complex baseband sampled streams, each at 1.25 MHz output sampling rate.

4. If all the above is correct, how do I guarantee absolute time alignment between the DACAB output and the DACCD output?

Thanks very much,  John Reyland

 

 

  • 0
    TI__Guru 68654 points

    Hi John,

    Regarding your questions:

    1. The DAC34H84 input bus allows 1.25GSPS of LVDS toggle rate. In DDR operation, this means the I bus has 625MSPS of data rate and the Q bus also has 625MSPS of data rate. You can think that the maximum DATACLK speed going into the device is 625MHz with data latched on both edges.

    The maximum bandwidth of the signal is limited by the 1st stage half-band interpolation filter. The low pass filter response is about 0.4*Fdata, which means this gives you about 0.8*Fdata of complex signal bandwidth. (i.e. 0.8*625MSPS = 500MHz BW). If you would like wider bandwidth, you can consider the DAC34SH84 with 750MSPS of data rate per channel.

    2. Yes, channel CD operates the same fashion as channel AB.

    3. yes, the final DAC update rate after interpolation will be 2x Fdata, or 1.25GSPS max.

    4. As long as you can assure that channel AB and channel CD data are loaded into the DAC with the same alignment, and both AB and CD channels have the same digital settings, the DAC output of each channel will be synchronized by design (same latency for both channel AB and CD). 

    -KH

  • 0 in reply to Kang Hsia
    Prodigy 50 points

    Hi KH,

    Thanks very much for your helpful answer.   Does the DAC34SH84 have maximum 750MHz maximum DATACLK rate?

    I could not find this important number on the data sheet.  Is it there in some subtle way or is this an omission on the data sheet?

    Thanks,

    John Reyland

     

  • 0 in reply to John Reyland
    TI__Guru 68654 points

    Hi John,

    The input LVDS bus specification can be found on page 10 of the datasheet. The LVDS bus specification has the LVDS toggle rate, data rate per DAC, as well as the necessary LVDS swing information. Typically, the min and max specifications are located in the electrical characteristics table. 

    -KH

  • 0 in reply to Kang Hsia
    Prodigy 50 points

    OK, I see.  Thanks very much

    New question please:  I am interested in buying a TSW30SH84EVM evaluation module for the DAC34SH84.  However, I would like to know the frequency and phase response of the low pass filter between the DAC outputs and the corresponding TRF3705 upconverter.  Could not find this in any documents on ti.com.

    Would you tell me something about this filter please? 

    Thanks,

    John Reyland 

  • 0 in reply to John Reyland
    TI__Guru 68654 points

    Hi John,

    The low pass filter is a 430MHz 3rd order Butterworth filter. The attached TI TINA file shows the circuit and simulation results. (You can download the TI TINA Spice simulator from our TI web.) We have to make the filter generic enough since there are many possible ways to evaluate this EVM.

    -KH

    DAC348x_TRF3705.TSC
  • 0 in reply to Kang Hsia
    Prodigy 50 points

    Hello Kang,

    Thanks for the interesting info. about the TSW30SH84 Evaluation Module filter response.  One more question please.

    Referring to the photo of this eval module on www.ti.com/tool/TSW30SH84EVM  "Complete RF Signal Chain Evaluation Module" ,

    each of the 4 DAC outputs seem to go directly to a tiny transformer.  These transformers are not on the schematic between the DAC outputs and the low pass filter inputs.   Are these transformers for balanced/unbalanced or vice-versa?  I appreciate any insight you can provide about these.

    Thanks,

    John Reyland

  • 0 in reply to John Reyland
    TI__Guru 68654 points

    Hi John,

    I believe that you are referring to the TC1-1-13 1:1 balun between the DAC output and the modulator input. They are shown on the TSW30SH84EVM schematic page 4 and 5. We placed the balun after the low pass filter to rebalance the signal before going to the modulator. Some of our customers' feedback is that it provides slight improvement to higher order harmonic distortions at high output frequencies. 

    -KH

  • 0 in reply to John Reyland
    Prodigy 50 points

    Thanks again for the help ful information,

    Another question please about the photo of the TSW30SH84EVM  eval module on www.ti.com/tool/TSW30SH84EVM  "Complete RF Signal Chain Evaluation Module" .  I noticed that the traces between the card's digital interface and the DAC data input bus seem to be very carefully constructed  How precise do we need to be in phase matching the 32 digital data inputs to the DACs?  Do we need exact (.001" tolerance) for trace lengths with 1.5 Gsamp/sec double clocked data inputs? Can we route traces to different layers and then back up again if we maintain the same length, or does the via length matter a lot? 

    We want to design the DAC34SH84 into a multiple output transmitter so of course we are looking carefully at how TI constructed their eval card.

    Thanks very much,

    John Reyland

     

  • 0 in reply to John Reyland
    TI__Guru 68654 points

    Hi John,

    On the TSW30SH84EVM, the LVDS traces are matched to within 10mils of each other. You can use 1mil tolerance, but the cost of the PCB may increase dramatically. Assuming FR4 material with approximately 120ps of delay variation per 1 inch of trace, 10mil of variation should not affect the timing drastically. 

    Since we have board area constraints, we have routed the 32-bit bus + clock and controls signals throughout the top, bottom, and the inner two power layers. We asked the board shop to control the impedance to with 10% tolerance and they are sufficient for our timing. 5% tolerance is also available with additional cost. 

    You can check out our design package, which includes the schematic and PCB layout file in the following link:

    http://www.ti.com/litv/zip/slac517a

    We uses Allegro for layout, so if you need .brd file, I can upload the file as well. Thanks

    -KH