ADS5409 SYNCOUT seems to be a data output bit

Hi,

Yes, from the description of the SYNC function you should see the SYNC output have a rising edge every 32 samples.   Have you checked the timing of the SYNC input relative to the sample clock?  The SYNC input needs to meet a certain setup and hold time around the rising edge of the sample clock.  The ADC uses the sample clock to latch the SYNC input and if the SYNC input is seen to have gone from 0 to 1 then the sync counter is reset and the next time the sync input is seen to have gone from 0 to 1 it needs to be 32 sample clock rising edges from the last time.  If the setup and hold time of SYNC into the ADC is not met relative to the sample clock then the ADC might 'see' the sync input sometimes be 31, 32, or 33 samples away from the last time. 

If the timing of SYNC is good, then may i please see screenshots from an oscilloscope of the SYNC input with sample clock, and the SYNC output?    

Also - check to make sure that the SPI programming hasn't turned off the SYNC input buffer (register 38) or disabled the SYNC mode (registers E and F).

Hello,

Thank you for your suggestions. I believe that my set-up is already correct, but I join scope sreen shots for your careful review. The measurements where made with a Agilent DSO-X 4104A (4 CH, 1 GHz, 5 GS/s) scope and 2 differential probes 1130A (1.5 GHz). On the screen shots, the green trace is the SYNC signal, which is also the trigger. The skew between the 2 probes was removed. The sign when probing was also checked to avoid 180 degree phase shifts.

ADC3112_CLKIN_SYNC.png: SYNC and CLKIN, showing the proper set-up and hold time.

ADC3112_DACLK_SYNC.png, ADC3112_DBCLK_SYNC.png: DATA clock relative to SYNC

ADC3112_SYNCOUT1_SYNC.png, ADC3112_SYNCOUT2_SYNC.png: SYNCOUT1 and SYNCOUT2 signals relative to SYNC. One can seen a data like pattern, changing with the analog input signal. If no signal is applied (0V), the signal is most of time constant, "0" or "1".

I have also attached the ADS5409 register configuration for your inspection.

My guest is that the SYNCOUT pins are multifunctional (but undocumented) and I have the wrong selection.

Regards,

Hi,

I have the lead designer looking at this now - he had been out of office until today.  I wanted to make sure with him that it is indeed the rising edge of sample clock the catches the syncin and it is.  I am not aware of any multi-function outptu choices for this pin, but it is something that we do sometimes so i have asked that of the designer too.  I will post back what i can find out.

Regards,

Richard P.

Hi,

It looks like there is a bit in the register space that needs to be set to enable the syncout, and the datasheet editor did not include the bit in the description.  Probably he expected the default state of the bit to be for normal usage which would be the syncout case.   It *is* a multifunction pin, but not in the normal sense that there is another function you might want to use in practice.  The other output for this pin is used in production test and would not be of interest in the datasheet, but that was made the default case after reset or powerup.    Probably the best course of action is to make the datasheet say 'make this bit 1' all the time like some other bits in the register space are.

Anyway - please set bit D2 of address x01 to a '1' and see if that solves the problem.  

It is located between the Hp Mode 1 bit and the Data Format bit.

Regards,

Richard P.

Hello Richard,

You get it, setting this undocumented control bit change things! Now the SYNCOUT signal outputs as expected. We can now continue to test interleaving of 2 ADS5409. Probably not a lot of peoples have already tried this function before...

I would appreciate if TI could rapidly update the datasheet of the ADS54XX family, and document all these hidden controls bits. The paragraph on Auto Correction is also expected to be far more detailed, but this is already the subject of an other pending post.

Regards,

Jean-Luc Bolli

Hello Richard,
It seems I was happy too quickly! Working further with the SYNCOUT feature, I observe that the SYNCOUT signal resets not in relation with the SYNC signal. I have attached again scope screen shots:

ADC3112_CLKIN_SYNC.png: time relation of CLKIN with SYNC, no violation

ADC3112_SYNCOUT1_SYNC_casex.png: different relation SYNC with SYNCOUT1, after reloading the ADS5409 configuration, also attached

All happen as if the SYNCOUT signal is a divide by 32 of the CLKIN, but with no controllable reset. I have also tried the other Sync Select mode (register F, D15-D12) but I see no changes.

I would appreciate very much if you could deliver a detailed documentation of the SYNC logic.

Regards,

Jean-Luc Bolli

May be I should mention that I am an experienced IC and PCB high speed analog designer and could probably understand a documentation not formatted for publication!

Regards,

Jean-Luc Bolli

Hi,

I have gone through our internal design document and I do not see any other SPI register bits that would need to be controlled, so I have gone back to the lead designer again.  I will keep you posted.  (I also did not see a description of the SYNCOUT in that document that would fit with what you are asking for.)

Regards,

Richard P.

Hi,

I spent some time looking through the RTL code of the device with the designer.  It looks to me as if the sync input is not seen by the 5-bit counter that is sourcing the sync output.  The sync input is latched by the sample clock and upon seeing the latched sync input go from low to high, the sync out counter is loaded with a fresh count - else the counter just keeps on repeating its count.  If the sync input is not seen - then the sync out just keeps cycling with whatever phase relationship it was last loaded with. 

I don't see any other bits in the register space either in the data sheet or in the source code that can inhibit the sync input except the bits that can be used to turn off the LVDS input buffer for sync.  And your listing of the register contents do not turn off the buffer.  There isnt anything else in the design to affect it.

So, I see two things to check.  First, and probably least likely to be a problem, check that the level of the sync input is biased to the right level soo that the LVDS input buffer should see the signal.  The scope shots you sent are from a diff probe, which shows swing amplitude but not level.  The input common mode range for the sync in on page 9 of the datasheet is pretty tight.  If the signal were ac coupled and biased around ground for example then the input buffer might not see the transitions. 

Second, do you have the ability to change the sync input to sample clock divided by 64 rather than 32?  There is a fair bit of internal latency through the device on its use of the sync input - more than 32 clock cycles.  The designer ran simulations with sync input being sample clock/64 so that the sims would easily show the sequence of everything, and it *should* be the case the having the sync input be clock/32 would make no difference - but *i* have not seen the proof of that.  If you could try cutting the rate of sync input in half, that may tell us something pretty quick.

Regards,

Richard P.

Hello Richard,

The SYNC signal is produced by a LMK04803B output in mode LVDS. Each pin toggle between 1.05 and 1.450 V. As the 100 Ohm termination is within the ADS5409, this seems to prove that the physical connection is OK.

The SYNCOUT signal outputs always as 16 x "1" and 16 x "0", following the CLKIN period. This change not whatever the SYNCIN frequency is CLKIN/16, 32, 64, 128. No changes also by toggling control bit "SYNC_EN" from register 38.

Effectively, all happen as if SYNC is not seen by the ADS5409. Would it be possible that the pin pairs P9/N9 is not correct and should be for example P10/N10?

Did you already test and validate the SYNC behavior on the EVAL board?

Regards,

Jean-Luc

Hi,

Those are the correct pins listed in the datasheet.  If you were to compare to the ADS54T02 datasheet you can see that those pairs of NC pins are for functions related to triggering for that other device.  And I checked the schematics for our lab characterization board and P9/N9 are the pins used for sync in.

I will look into having either the EVM powered up on the bench for this function or see if the lab characterization board would be better. 

Regards,

Richard P.

Hi,

I have had the EVM powered up on my bench for the past week (or more) and have reproduced the issue that the syncout is not in a constant and expected phase relationship to the syncin.  I have had the characterization engineer look at it, as well as the design team.  The design team is looking into the issue.   I had suspected that the input buffer for the syncin was possibly turned off, but have been able to rule out that possibility.  The sync input is seen by the device.   There is a register that controls the starting value of the device by 32 counter so that the phase of syncout could be changed, but we only use the default power up setting for this.   And writing to this register seems to not have any effect, so this seems to be the root of the issue.  The starting value of the syncout divider seems to not be constant.   

I will have to wait for the design team to figure this one out.

Regards,

Richard P.

Have the question been solved? I run into the same problem to use 5 ADS5409.

Hi,

it'll take me a day or so to look up and sort through the email trail that pertained to this issue, so I'll do that and post a summary version. 

At a high level, there is a bit in the register space that enables the output sync pin to output SYNC instead of a bit needed for production test, and that enable bit didn't make it into the datasheet but will at the next revision of the datasheet.  That bit is bit 2 of the register Config1 to enable the output SYNC.

 But then there was something else that should not trip up anybody, but did when we tried to use a hidden feature to debug.  The output SYNC is a divide-by-32 of the sample clock, and there is an internal register that hold the starting value of the counter.  For multiple devices to be in sync, the starting value of all the devices should be the same and if the default value of this starting value is used in all devices then the devices should be in sync.  But the starting value of the counter is only loaded upon the assertion of that SPI register enable bit. 

 

So to keep all the devices in sync, have the input SYNC low, do a SPI write to all the devices to set the syncout_ena bit in register Config1 bit 2.   Then start the input SYNC signal to all the devices and make sure all the devices get the input sync signal at the same time - meeting setup and hold times around the sample clock into the ADC.  That should make all the ADCs output SYNC at the same time.   Every time the ADCs see the input SYNC go high the divide by 32 counter for the output SYNC is reset.  If the input SYNC is periodic with a period of a multiple of 32 clocks, then on every rising edge of the input SYNC it 'resets' the counter to the value it would be at anyway and the output SYNC remains at a period of 32 clocks.

Regards,

Richard P.

Hello,

So fare, I did not take the opportunity to try the above proposed fix, because we should put the project into "hold" mode in late 2014, due to our incapacity to get a solution at this time!

Fortunately, it seems the project will be reactivated within the next months, and I will post our results as soon as available.

Best regards,

Jean-Luc Bolli