DAC34H84 Configuration

Hello,

I did not notice anything that could cause the DAC output to be in the zero state. To make sure the DAC is operational, please enable the fine mixer (under digital tab) and also any of the coarse mixers (fs/2, fs/4, and fs/8). You will need to make sure the constant input is enabled under the input tab with appropriate digital code in the configuration. The easiest way for a most negative full-scale is to program the code to be zero with input code format as offset binary. You should be able to observe some basic CW tones in this setup. 

Since you have a TSW1400 setup, I would recommend that you start the testing with the default TSW1400 DAC34H84 firmware and also the default DAC34H84 configuration file. You can then modify the DAC settings to match your FPGA design. this will eliminate a lot of variables in your system design. 

-Kang

Kang,

Thank you for the kind reply. I have verified the DAC is operational by following your steps. I enabled a constant input, and enabled the course mixers. As expected, I received oscillating outputs of varying speeds as I changed the course mixer settings.

Moving on, I have loaded the default firmware for the DAC34H84 using HSDC Pro, and set up a basic configuration of the DAC based off of one of the configurations provided with the program. The configuration I started with was:

DAC34H84_FDAC_1228p8MHz_4xint_NCOoff_QMCoff.txt

I made a few modifications, as I did not have available an external clock anywhere near 1 GHz readily available. The only changes I made were to set the interpolation down to 2x, and setup the CDCE62005 to match the requirements. Attached is the configuration. With this setup, I get the warnings FIFO 1 away, FIFO 2 away, IO Test, and OSTR Pattern. However, I do not get any FIFO collisions.

Loading the default firmware into HSDC Pro, I create a single tone, and 'Send' it to the DAC. I chose a single tone at 10 MHz, with the sampling speed set the 62.5 MHz (specified from the CDCE62005 settings). With this configuration, however, I am still getting zero output on the DAC.

Thank you again for your time,

Nicholai

Kang,

I have tried one of the other default configurations provided with the DAC software. The configuration I am using is titled:

DAC34H84_FDAC983p04MHzPLL_2x_NCOoff_QMCoff_CDCE62005_VCO_983p04MHz.txt

In this setup, the PLL is enabled. They have an input divider of 5, feedback divider of 256. The output divider is set to 2. The PLL is set to double this with M=32, N =16. So, the DACCLK = 19.2 MHz * (256 * 32) / (5 * 16 * 2) = 983.04 MHz.

The VCO is at half of this, at 491.52 MHz. The FPGA clocks are set to divide by 8, and are thus at 122.88 MHz. I used custom TSW1400 firmware to confirm that this is the correct clock.

Next, I used HSDC Pro to load the TI firmware for the DAC34H84. I created a single tone at center frequency 10 MHz. The data rate is set to be 122.88 MHz- the FPGA clock. The DAC control and HSDC Pro are set to 2's Compliment. After all of this, I was expecting to see a sine wave at the output, but get nothing. Attached is a screen shot of HSDC Pro. The O-scope is connected to IOUT A2.

Nicholai,

With this setting, the DAC rate Fdac after 2x interpolation is 983.04MHz. The data rate before 2x interpolator is at 491.52MSPS. Therefore, on your HSDC PRO GUI, you should type in 491.52MSPS. 

With your previous setting of 122.88MSPS, 10MHz output, you should be able to see a 40MHz output after accounting the difference in data rate setting. This is assuming that you used the default HSDCPRO firmware, not your custom firmware.

Keep in mind the FPGA clock is not the same as the data rate presented before the DAC. The FPGA clock is running slower to account for the FPGA memory structure.

-Kang

Kang,

Thank you for your reply, again. I have verified what you have said, and it is correct. I changed the settings in the HSDC Pro, and see the sine wave as expected. I was able to alter the DAC settings to my own, and with the default firmware of the TSW1400, I can still get a sine wave. This makes me think that the root of my cause is the format of the data I am sending to the DAC via my firmware. A quick look at the data sheet, I am supposed to be sending data in the following form:

I am only currently working on channel A (eventually B, but not C and D). Thus, I only need data on the rising edge of the clock, and the data must be center aligned. Via my firmware, this seems to jive with my simulation:

Note, the data is 16-bits long, and it is wired to DAB. DCD is left high z (could that be my issue?). On the falling clock, the data is set to 0000- so I should get nothing on channel B. Using an O-scope, I can see the clock and my LSB, and verify that the data is indeed center aligned to the rising edge of the clock:

It seems as if the data is formatted properly (offset binary, sine wave), but I clearly must be missing something. Any ideas?

Thank you for the help thus far, it is been extremely useful.

Nicholai,

I am glad to hear that you got the baseline setup going. 

Regarding your questions:

Nicholai L'Esperance1 said:

I am only currently working on channel A (eventually B, but not C and D). Thus, I only need data on the rising edge of the clock, and the data must be center aligned. Via my firmware, this seems to jive with my simulation:

Yes, this is correct. You will need to use rising edge of dataclk to latch in channel A data.

Nicholai L'Esperance1 said:

Note, the data is 16-bits long, and it is wired to DAB. DCD is left high z (could that be my issue?). On the falling clock, the data is set to 0000- so I should get nothing on channel B. Using an O-scope, I can see the clock and my LSB, and verify that the data is indeed center aligned to the rising edge of the clock:

It is OK to leave DCD as high Z for now since you are not observing the output at this point. (You may get some random toggling of the output due to the noise at the input triggering the output state. The output should have very small noise though)

Nicholai L'Esperance1 said:

It seems as if the data is formatted properly (offset binary, sine wave), but I clearly must be missing something. Any ideas?

At this time, I would check all the signal levels conforms to the LVDS standard. The clock that you have shown in the post has level from 0 to 3. I am assuming that is related to voltage? If so, you may have configured your driver from the FPGA as LVCMOS instead of LVDS.

-Kang

Kang,

Thank you for the response, and I apologize for the late reply.

Kang Hsia said:

At this time, I would check all the signal levels conforms to the LVDS standard. The clock that you have shown in the post has level from 0 to 3. I am assuming that is related to voltage? If so, you may have configured your driver from the FPGA as LVCMOS instead of LVDS.

What I did show was a signal going from zero to three volts. The reason is I am duplicating the signal going to the DAC, and using this duplicate to measure on one of the SMA ports using 3.3-V LVCMOS. The signals going over the bus to the DAC are all sent using LVDS. To duplicate the signal, I'm simply running second ALTDIDO megafunctions since they do not support fan-out (and this way I can be sure I'm not loading down anything going to the DAC).

I am getting output, just not what I want. Maybe its my bit file, but it seems to be what I want in the simulation. To help troubleshoot, I'm passing the output of a 16-bit counter directly into the ALTDIDO megafunction, expecting to see a ramp. However, I'm getting not what I want. Take a look below:

The reason I suspect there is an issue with how I'm sending the bits is when I make the counter count down instead of up, the output exactly flips. See below:

My first thought was, perhaps the data is set to 2's Compliment, instead of offset binary. This was not the case. I've also tried reversing the bus from the DAC control panel, but this seems not to be the issue either.

Kang,

Sorry for the multiple replies, I'm spending a lot of time on this and don't want you to waste time answering things I've solved. I seem to have the DAC in a working state again. I reset the DAC, reseated all the connections, checked the jumpers, etc etc, and have it functioning again. I guess this leaves me with only a few minor questions. My first is- is this DAC always noisy? Even using custom firmware, the generated sine waves are pretty poor quality. Below is a screen of two tones generated by HSDC Pro and synthesized:

I have the same problem with custom firmware (here I have two waves added with different frequencies):

Is this standard performance of the DAC?

My second question is this- when giving a ramp to the DAC, the output appears to be saturating, even at higher frequency ramps. Take a look below, where I have a triangle wave.

Do you think this is simply because of the inductive coupling on the output? Even at higher speeds I can't get a good looking triangle wave. 

Thanks for your time!

Just to add a little more info- It is not really noise I'm looking at, but something else. Here is a zoomed in plot on one of the sine waves:

Notice, the frequency of the 'noise' is not a multiple of the clock. It's at about every 2.5 clock cycles. The clock is about 62.5 MHz, this distortion is about 25 MHz.