ADC12J4000EVM GUI enabling of adc_pat_en

Hi Marc

That test pattern mode is most useful in the ADC12J4000 DDC Bypass mode of operation, where raw 12 bit ADC data is available. In the DDC modes the best way to evaluate link operation using full 16 bit sample data is with the Long Transport Test pattern mode.

Unfortunately the bit to enable the ADC Test Pattern is not accesible directly in the current version of the EVM GUI. It will be fixed in the next version in the works. To enable it in the meantime you can use the Low Level View tab in the EVM GUI to load the attached .cfg files.

0753.ADC12J4000_EN_ADC_TPM.cfg

2526.ADC12J4000_DIS_ADC_TPM.cfg

One file enables the test pattern, the other disables the pattern. Copy these files into the following folder location:

C:\Program Files (x86)\Texas Instruments\ADC12J4000EVM GUI\Configuration Files

Use the Load Config button to select and load the desired file.

Let me know if you have any problems getting this to work.

Regards,

Jim B

What should I expect for a long transport pattern when in decimate by 10 mode with DDR? The spec only talks about decimate-by-4. However, I cannot get decimate by 4 running w/P54 =1 (I can't get any of the P54 cases operational).

I am using the ADC12J4000 EVM GUI and I am setting up the Xilinx JESD core with: F = 2, K = 12, L = 2.

The pattern I am receiving from the Xilinx JESD core is: (repeating)

0080 0080 0080 0080

0080 0080 0080 0080

0080 0080 0080 0080

0080 0080 0080 0080

0080 0080 0300 0300

Ramp pattern seems to be operational. Real data does not appear correct as compared to the TSW + EVM platform output.

Hi Marc

I am attaching the expected output data for Decimate by 10 DDR in Long Transport Test Pattern mode:

6837.Dec_10_DDR_Long Transport Pattern Output.xlsx

Please let me know when you received your ADC12J4000EVM.

If it is a very early version the P54 mode may not be supported. You can also use the ADC12J4000EVM GUI to check the device revision. Using the Low Level Tab, select the ADC12J4000 and the register CHIP_VER. Then click on the Read Register button in the lower left. Let me know what the value read back is.

Best regards,

Jim B

Hi Jim -

When I read the CHIP VER value, I get 2.

Comparing the Xilinx JESD core output to your expected output, I am missing transport layer information (I am looking at Xilinx's data output bus on the core). Do you have register programming information for Xilinx's JESD204B core when the ADC is operating in this mode (dec by 10, ddr)? It looks like I can program values for L, F and K only (L=2, F=2 and K=12).

Regards,

Marc

Hi Jim -

By changing the LMFC value on the Xilinx core from 1024(default) to 512, I am now able to receive the expected long transport test pattern correctly. However, I am not seeing the correct data from the ADC when running in normal mode. I have offset binary selected on the ADC, but it appears to be coming across as signed 2's complement:. If I change to signed 2's complement, or if I set the NCO to 2.8 GHz, little or no change with the received data:

0002 0010 ffec ffed, 0006, etc .....

I am using the ADC12J4000EVM GUI software, v1.3, to initialize the ADC on the start of every capture. If long transport is operational, i would expect that we are ready to capture ADC data over the JESD bus after restoring the 'normal operation' condition. Are there any additional enable bits that have to be set when switching from "long transport test" to ADC capture?

Regards,

Marc

Hi Marc

I'm glad you were able to make some progress.

Please note that the output data mode setting only has an effect in DDC Bypass (12 bit data) mode. In the DDC modes with decimation the data is always formatted as shown in section 7.3.6.4 of the datasheet.

What if any input signal are you applying to test the device when operating in Decimate by 10 mode? The on-board balun is designed support input frequencies of 400 to 3000 MHz, so the signal should be in that frequency range, and around 0dBm to -10dBm at the RF generator output.  I would recommend setting the NCO to a frequency that is 10 MHz higher or lower than the input signal. This should result in an output waveform of approximately 10 MHz.

When switching from the test pattern mode to normal data mode, you just need to first disable the JESD204B Block, change the test pattern setting to normal mode and then re-enable the JESD204B Block. No other settings need to be adjusted.

Best regards,

Jim B