ADS42LB69 Clock Input DC-coupled

Hi Masa

The device performance is only specified for an ac-coupled clock.

The clock amplitude is specified in the CLOCK INPUT section of the RECOMMENDED OPERATING CONDITIONS table on page 3 of the datasheet. Since the clock duty cycle must be in the range of 35% to 65% (the clock cannot be static high or static low) there is no reason to DC couple the clock source to the clock inputs.  

Regards,

Jim B

 

Hi Jim,Thank you very much for your answer.Masa

Hi Jum,

I have another question got from your explanation.

"Since the clock duty cycle must be in the range of 35% to 65% (the clock cannot be static high or static low)"

Can clock be stopped when it was not used?

I got  "Yes" at the another E2E question and answer below.

http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/p/376025/1345820

Best regards,

Masa

 

Hi Jim,

Thank you very much for your answer. I understand that stopping clock is no problem.

and I would like to confirm that the following your message is a general comment or ADS42LB69 can use/should use DC coupled clock?

"Therefore to provide a clock source that can reliably stop in a logic 0 or logic 1 state, and provide good device performance when active, a DC coupled clock source should be used."

Best regards,

Masa

Hi Masa

In general customers wish to stop the clock to an ADC to minimize the power consumed by the device, and stop output data and data clocks.

If the input clock is AC coupled then there is a good possibility than once the AC-coupling capacitors de-bias the differential plus and minus inputs will be at approximately the same voltage. In this condition the clock receiver may trigger on any small amount of noise present on those inputs. If this unpredictable clocking is OK in the application then AC coupling should be maintained.

If unpredictable clocking cannot be tolerated in the application then the clock inputs must be DC coupled. 

If a DC coupled clock connection must be used then it is very important to match the common mode voltage of the clock source to the common mode voltage of the clock receiver. If the common mode voltage is matched properly and duty cycle is maintained within datasheet limits performance should be OK.

Best regards,

Jim B

 

Hi Jim,

Thank you very much for your kind explanation. 

Best regards,

Masa

Hi Jim,

May I have a question again about the common-mode voltage RANGE(min and max) of the dc-coupled clock input? 

The clock input source will be designed to match the internal bias leve of the clock receiver.

I am refereing CLOCK INPUT section (on page 60 of the datasheet) indicating typical 1.4V.

 

Best regards,

Msaa

Hello Jim,May I have your answer? Masa

Jim,
May I have your answer?
Best regards,
Masa

Hi Masa,


For best performance, we do not recommend DC coupling to the clock input for this device.
The common mode for the clock input is generated internally and the device has been characterized only under conditions where the clock is ac coupled.
DC coupling to the clock input is not supported for this device so we have not characterized min/max of the clock common mode or the current sourcing/sinking capabilities of the clock input to allow successful dc coupling without degrading performance.


Thanks,
Eben.

Hi Eben,

Thank you for the answer.

Masa