ADC12J4000 JESD link errors

Hi Zanzibar

What ADC12J4000 operating mode are you using? What are the values of D, DDR, P54, K as referenced in Table 10 of the datasheet.

What is the ADC DEVCLK frequency?

Which FPGA capture solution are you using? Is your design based on TI example code or your own new design?

Can you attach data capture files for the low signal and larger input signal cases?

Best regards,

Jim B

Hi Jim,

- What ADC12J4000 operating mode are you using? What are the values of D, DDR, P54, K as referenced in Table 10 of the datasheet.

D : 1 (DDC bypassed)

DDR : 1 (DDR Rate)

P54 : 0 (5/4 PLL Disabled)

K : 32

- What is the ADC DEVCLK frequency?

4GHz

- Which FPGA capture solution are you using? Is your design based on TI example code or your own new design?

We use a FPGA Xilinx Virtex 7 690T. We have our own design built around the Xilinx GT Wizard for the GTH management, and the Xilinx JESD204 IP for the JESD management.

- Can you attach data capture files for the low signal and larger input signal cases?

Please find attached the excel file with a 10MHz sinus captured at 4GHz at both -20dBFS and -2dBFS of amplitude. Notice that the JESD204 link down issue appears on the –2dBFS capture (sample 3360).

More :

• Sampling clock = 4GHz from an onboard clock synthesizer
• GT Ref clock = Fs/8 = 500MHz
• Sysref = Fs/1024 = 3.9MHz always running
• FPGA = Xilinx Virtex 7
• ClkGen Control 0 (0x30) :

 Typical ADC configuration:

Sysref receiver disabled

Sysref processor disabled

• DDC Ctrl register (0x200) :

Format = signed 2s complement

Dmode = bypass

• JESD Control 1 register (0x201) :

Scrambler disabled

K = 32

Serial rate = DDR

• JESD Control 2 register (0x202) :

5/4 PLL disabled

JESD204B Test mode disabled

When performing a signal acquisition, the JESD204 link regularly goes down, resulting in a loss of data. We have a good idea of what’s going on when the link goes down by instrumenting the FPGA firmware around the GT module.

At some point, for some reason, a link start to produce consecutives not_in_table symbols with disparity errors. After about 10 consecutives wrong symbols, the JESD module send a comma alignment request to the GT.

When the alignment process is done, we are again able to receive ADC datas.

The problem can occur on any of the 8 serial links.

The same problem is observed on each of our 4 ADCs.

 We did many measurements to validate the physical communication channel. We have a perfectly opened eye diagram. PRBS7, PRBS15 and PRBS23 tests are received by the GT without any error.

 The Ramp test pattern and the ADC Test pattern are received without any error only when the scrambling is disabled. Enabling the scrambling after the test generator causes errors as described above.

 A noise acquisition or a very low signal acquisition (below -20dBFS) are received without error when the scrambling is disabled. Errors start to appear when we increase the amplitude of the input signal.

When the scrambling is enabled, every signal acquisition causes errors.

Thanks for your help,

ADC12J4000_capture.xlsx

Hi Zanzibar

Please confirm you are setting the ADC12J4000 KM1 (K Minus 1) setting to 31, to achieve K=32.

Also, my calculations for that configuration give a SYSREF frequency of 3.125 MHz.

Fbit = 8Gbit/sec, Tframe = 80 bits, therefore Fframe = 100 MHz

Fmultiframe = Fframe/K = 100MHz/32 = 3.125 MHz.

Can you share the schematics for the ADC related signals including the data link and clocks to the FPGA?

Best regards,

Jim B