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ADS4129 LVCMOS Output Impedance

Steven Hamilton
Prodigy 10 points
Other Parts Discussed in Thread: ADS4129

I'm currently working on a circuit design involving the ADS4129 ADC. I'm attempting to output it's data in the LVCMOS mode and run my traces from it to an FPGA I'm working with, but I can't find the output impedance of the ADS4129 on any documentation. I see, over and over, the LVDS output impedance is 100ohms but nothing about the output impedance when run in LVCMOS. Is it 100ohms as well? Or 50ohms like the typical standard? Thank you for any help you may provide.

  • 0
    TI__Genius 17290 points
    Hi Steven,

    For the case of ADC CMOS outputs, we typically don't concern ourselves with impedance matching. The main reason is that we expect the routing from the ADC to the FPGA is fairly short, perhaps just a couple of inches. If longer traces are used then we increase the EMI noise in the system by increasing the inductive loop. Also, the longer the traces, the more load capacitance we have. This load capacitance requires more current from the ADC (i.e. a current spike) which will cause additional loading on the ADC's power supply and potentially "ground bounce" inside of the ADC. You can imagine that if noise is injected onto the ADC's ground (which has some parasitic inductance to the board's ground) then the ADC's analog performance will start to suffer and a higher noise floor and lots of additional spurs can be observed. This also explains why we don't want to terminate the CMOS outputs, because a termination to ground would require much higher currents from the part. If 50Ω to ground was used on each output, we would have 32 mA sunk to ground when the output was high at 1.8V. With 12 data bits and a clock, we would have nearly 500 mA of current sunk to ground when all signals are high. If we assume 50% duty cycle, then the additional power would be 1.8V * 250mA = 450 mW. Nearly twice the power of the ADC!

    If you must use CMOS and need to drive more than a couple of inches, then we recommend using a CMOS buffer that is placed very close to the ADC. This limits the current that the ADC must output and pushes any ground bounce issues to the CMOS buffer where the analog performance will not be affected. And in most cases, you can also use series resistors (~20Ω or so) to limit the current draw from the ADC - with a slight degradation in the slew rate of the signals. We typically use 50Ω traces on the EVM.

    For most applications, we recommend the use of LVDS outputs. The differential outputs eliminate both power supply and ground noise issues in the ADC and limits the EMI noise in the system. You can also drive longer distances while still maintaining good signal integrity because the LVDS standard is properly terminated.

    Regards,
    Matt Guibord