DAC38J82 buswidth of SERDES and lane config

Hi Weiqiang,

The buswidth isn't the issue - remember that for each lane we're serializing the data into a single bitstream and then deserializing back to parallel data. The FPGA, with a buswidth of 40-bits, takes 40 bits (4 octets) and serializes them up to a single stream at 40 times the parallel clock rate. The DAC, with a buswidth of 20-bits, takes 20-bits at a time from the serialized stream and deserializes to a parallel clock at 1/20th the linerate. This just means that the DAC clock runs twice as fast as the FPGA clock.

I suspect your JESD clock divider is not set correctly if you're skipping samples. This could happen if the JESD clock divider is set to double the correct value. This may be fixed by setting the JESD clock divider to half the divide ratio (e.g. if you have divide by 4 set, change to divide by 2). Please download the DAC38J84EVM GUI and use the Quick Start feature to check the rest of your settings.

Regards,
Matt Guibord

Hi, Matt

I tried your suggestion but it is not working, but I manage to achieve the dac output rate by doubling the JESD clock at the FPGA side and change the FPGA  input from

tx0_tdata  <= { tp_dac_i[0][15:8], tp_dac_i[1][15:8], tp_dac_i[2][15:8], tp_dac_i[3][15:8] } ;  
tx1_tdata  <= { tp_dac_i[0][7:0],  tp_dac_i[1][7:0],  tp_dac_i[2][7:0],  tp_dac_i[3][7:0]  } ;

to

tx0_tdata  <= { tp_dac_i[0][15:8], tp_dac_i[0][15:8], tp_dac_i[1][15:8], tp_dac_i[1][15:8] } ;  
tx1_tdata  <= { tp_dac_i[0][7:0],  tp_dac_i[0][7:0],  tp_dac_i[1][7:0],  tp_dac_i[1][7:0]  } ;

e.g., increase clock twice and reduce dample rate twice, so every two sample with the same value. it looks OK from the dac output without interpolation filter, but if interpolation is applied , the wave looks not so clean.

is this OK?

Hi Weiqiang,

Please find a configuration file attached.

DAC38J82_300Msps_8x_421.cfg

Regards,
Matt Guibord

Hi, Matt

the following is the 3 pics I captured from a scope.

the top one is with interpolation 8,

the middle one is with interpolation 4,

the bottom one is no interpolation or interpolation1.

the DAC clk =2.4G ( I replace the osc on EVM with a 100MHz part), the DAC input data rate = 300Msps. the sine waveform is generated in FPGA with T = 300M/16 = 18.75Mhz.

so it looks the filtered signal is not so correct, is this the filter setting problem or the SERDES setting problem? I tried to attach the EVM cfg file but not sure it OK or not.

DAC3XJ8XEVM_vco0_75m_dac2_4G_IF600m_jesd150m.cfg

Hi, Matt

as you indication,

"Note that you can't just change the interpolation setting on the DIG BLOCK 1 tab, since all of the clocking needs to change as well - thus the point of the quick start procedure."

so may I know how to configure these clock registers? I checked the related registers config37 and config59 and config49, any other register to check? for example, if interpolation 8x is chosen (config0 = 0x418), what is the clock to the FIR filters? how to configure?

I think it is controlled by clock distribution circuit inside.

best regards

weiqiang

Hi Weiqiang,

Correct, it is controlled internally by a clock distribution circuit in the chip. The internal dividers are set based on the interpolation setting, however you also need to change the serdes reference clock divider and JESD clock divider. Please use the GUI quick start tab. It will automatically calculate the DAC clock dividers based on your data rate, JESD configuration, and interpolation.

Regards,
Matt Guibord

Hi, Matt

so may I know the relationship between "JESDCLK" and "SERDES CLK" on the "Clocking" tab of DAC3XJ8X GUI ? is Fdata = JESDCLK?  if I select the wrong clock the FIR will be wrong.

my current target Fdata =300Msps, and I assume DACCLK = Fdac = 2.4GHz.

Hi Weiqiang,

The quick start tab will automatically choose the clock dividers for you, so that you don't have to.

The JESD clock divider is set by:

JESDCLK_DIV = Interpolation*L/M

L = number of lanes (1,2,4,8)

M = number of DACs (2, 4)

Regards,
Matt Guibord

Weiqiang,

Can you confirm that you're setting up the quick start as shown below? You should not change any other parameters in the DAC GUI.

In HSDCPro you should select "DAC3XJ82_LMF_421" for the DAC and set the data rate to 368.64 Msps. The data format is 2's complement.

Regards,
Matt Guibord

Hi, Matt

I think I got the idea, and my design looks OK.

it looks that the relationship of  "DAC Output Rate" =  "DAC Data Input Rate" x "Interpolation". 

So if "Interpolation"  is changed, the DAC clock must be changed accordingly, is this correct?

anyway, thanks a lot.

weiqiang

Hi Weiqiang,

Correct. You'll also need to change the serdes reference divider and JESD clock dividers by the same amount.

Regards,
Matt Guibord