DAC37J82 register settings

Scott Greeley1

Other Parts Discussed in Thread: DAC37J82, DAC38J84, LMK04828

We are using the DAC37J82 on a custom card.    I’m going thru its datasheet, and have several questions regarding its register settings. I've tried using both the DAC3XJ8X and TSW3XJ8X software, but they don't offer much insight for some of the register settings.

Our application is summarized as follows:
- 240MHz DACCLKp,n ref clk input
- using the onboard DAC PLL configured to 4320MHz, P=3, M=6, N=1
- DAC output rate = 1440MHz
- with SERDES PLL = 1800MHz using the PLL (DAC) clock as input (MPY = 5, REFCLK_DIV=4).
- We have a several bandwidth, lane variations we’re considering, and will configure their L-M-F-S-HD and RATE accordingly.
   a) 2-lane, 180MHz input data rate, interpolation = 8, 3600Mbps SERDES line rate -- configured as 2-2-2-1-0 and half RATE
   b) 4-lane, 180MHz input data rate, interpolation = 8, 1800Mbps SERDES line rate -- configured as 4-2-1-1-1 and quarter RATE
   c) 4-lane, 720MHz input data rate, interpolation = 2, 7200Mbps SERDES line rate -- configured as 4-2-1-1-1 and Full RATE

- What LB setting is recommended for SERDES VCO clk of 1800MHz using DAC clk (1440MHz) has it’s input reference?
- What should the clkjesd_div setting be?   It's used for JESD clock, but datasheet doesn't mention what rate it should be.
- How do we determine the pll_vcoitune and pll_cp_adj settings?
- Some of the registers are labeled with ‘FUSE controlled’.    Do these registers require any special consideration?

Thanks.

over 8 years ago

0 Kang Hsia over 8 years ago

TI__Guru 66184 points

Hi Scott,
let me look into this and get back to you.

-Kang

0 Kang Hsia over 8 years ago

TI__Guru 66184 points

Hi Scott,

Please see attached powerpoint presentation regarding the on-chip PLL configuration for your applications. I have also included the settings needed for the SERDES block and the JESD block.

For the fuse-controlled registers, please be sure to toggle the CMOS RESTB signal upon starting upon. This is required to ensure the device load the correct upon at start-up

DAC37J82 Settings.pptx

DAC37J82_2x_720MData_4lane_421mode_Fdac1440MHz_onchipPLLenabled.cfg

DAC37J82_8x_180MData_2lane_222mode_Fdac1440MHz_onchipPLLenabled.cfg

DAC37J82_8x_180MData_4lane_421mode_Fdac1440MHz_onchipPLLenabled.cfg

0 Scott Greeley1 over 8 years ago in reply to Kang Hsia

Intellectual 585 points

Thanks Kang.

What is the purpose of the JESD clock, and how is the JESD clock divider determined (clkjesd_div of CONFIG37) ? The divider seems like it's a function of the number of SERDES lanes and interpolation factor, but this isn't documented in the data sheet or EVM software.

0 Kang Hsia over 8 years ago in reply to Scott Greeley1

TI__Guru 66184 points

Hi Scott,

The JESD clock is a divided-down digital clock used to handle all the JESD IPs within our DAC37J82. I agree that the datasheet need to be updated to reflect the JESD clock setting. Currently, we have to refer our customers to the GUI so a correct, calculated result can be derived. This section will be updated on the next version of the datasheet.

-Kang

0 Scott Greeley1 over 8 years ago in reply to Kang Hsia

Intellectual 585 points

I've run the DAC3XJ8X GUI v1.1 in SIMULATION mode (we don't have an eval baord) for our 2-lane, 180MHz DAC input rate, 240MHz DAC clk ref case. After entering configuration on the Quick Start tab, the 'Clocking' tab is suggesting DAC PLL's Prescaler =2 and M Divider =1, even after enabling the DAC PLL. These aren't valid for using the DAC PLL. Is this a bug?

Could you clarify a few things for the DAC37J82: It should only have one JESD Link, correct? Which SERDES PLL (0 or 1) is active?

Also, is it acceptable to just follow DAC37J82 datasheet section 8.3 to determine which registers need to be changed (and the order they're written), AND to leave the remaining registers at their default value?

thanks,
Scott

0 Kang Hsia over 8 years ago in reply to Scott Greeley1

TI__Guru 66184 points

Hi Scott,

You can use the three configuration files (.cfg files) that I had attached earlier and load them into the DAC GUI. Simply go to low level view > load config > select the file that you want to load. Under the clock tab, you should see the correct settings that I had verified in the lab. I just tried it in simulation mode and the desired mode got loaded.

The DAC37J82 should only have 1 JESD link. The SERDES PLL (0 or 1) is controlling the SERDES receiver. SERDES-0 is the RX lane0 to lane3 block, while SERDES-1 is the RX lane4 to lane7 block. You may pick and choose the RX lanes among the two blocks depending on your PCB routing. Depending on the RX lanes being enabled or not, each SERDES block and the corresponding SERDES PLL will be enabled. (Note that the config that I have send you have these mux implemented to facilitate our EVM layout between TSW14J56 and DAC38J84 EVM).

Note that there is an internal mux that routes the desired RX lane to the internal JESD lane. The config is in config95 for the mux. For instance, you could have RX lane6 and RX lane7 active and route the RX data to JESD lane0 and JESD lane1.

The datasheet section 8.3 is a good start. Some of the key points are to be sure to toggle the CMOS RSTB pin to initialize the DAC + fuse logic. Also, pay attention to register 0x4A on when to reset the JESD block. You will need to make sure all the configuration are complete before reset the JESD block. Other registers can be left along if the mode matches the default start-up value.

Please advise if you need multi-DAC chip synchronization. We may need to modify the sequence slightly depending on your synchronization goal. In this case, we may also need to review your sysref triggering (which may come from our LMK04828 chip or some other chip that you have).

-Kang

0 Scott Greeley1 over 8 years ago in reply to Kang Hsia

Intellectual 585 points

Hi Kang,

Could you confirm that the sequence below for configuring the DAC is okay? I'm waiting appr. 5 msec between each step, and between register writes.

1. set the DAC Sleep pin to low (brings it out of power down mode)

2. toggle the DAC RESETB pin low and then high (resets the DAC's registers to default values)

3. write CONFIG74 register such that bits 4:1 are all 1's, and bit 0 is 0. (Puts JESD block in INIT state and in reset.)

4. write all DAC37J82 registers of the .cfg file, in the order listed

5. write CONFIG74 register such that bits 4:1 are all 0's. (brings JESD block out of INIT state)

6. write CONFIG74 register such that bit 0 is 1 (brings JESD block out of reset)

7. clear the alarms by writing to CONFIG108 register

8. read CONFIG108 register -- > the lowest 4 bits read back as 6, indicating DAC PLL and SERDES PLL block0 are locked

9. read CONFIG49 register -> the lowest 3 bits read back as 3 or 4, indicating the loop filter voltage is centered

thanks,

Scott

0 Kang Hsia over 8 years ago in reply to Scott Greeley1

TI__Guru 66184 points

Hello Scott,

The steps look fine. Please see attached for more detailed start-up sequence. I plan to update the datasheet with the sequence attached.

-KangDAC38J84 Start-up Sequence.docx

0 Scott Greeley1 over 8 years ago in reply to Kang Hsia

Intellectual 585 points

Hi Kang,

We are using a single SYSREF pulse that will occur at Step 17 of your Start-Up Sequence document.

Are Steps 8 b,c necessary for our application, since we only have the one SYSREF pulse?

Your Start-Up Sequence document lists very specific steps (9-15) for writing the DAC settings. Just to confirm, is it acceptable to write the settings in numerical order (CONFIG0, CONFIG1, ... , CONFIG125)? -- as indicated in Step 4 of my previous posting.

thanks,

Scott

0 Kang Hsia over 8 years ago in reply to Scott Greeley1

TI__Guru 66184 points

Hi Scott,

Good point. If you only have one SYSREF pulse, then you can arm the initialization circuits at step 8.

Yes, you can write the register in order. You just have to be aware to not overwrite certain initialization circuit register that need to be in certain sequence.

I will update the procedure and resend to you. By the way, are you AC coupling your SYSREF? If you only have one pulse, then you may need to DC couple the sysref since it may take some time for the DC bias to settle. If you are using the LMK04828 clock circuit, we have an interface network for LCPECL driver (low common mode of 0.5V) to our DAC sysref circuit. You may refer to our EVM schematic for detail.

-Kang

0 Scott Greeley1 over 8 years ago in reply to Kang Hsia

Intellectual 585 points

Kang,

We are AC coupled on SYSREF. We are driving the SYSREF from a Xilinx FPGA using an LVDS output. Note: the FPGA's specs are Vodiff = 350mV typ (247mV min, and 600mV max), with output common mode voltage of 1.25V typ (1V min, 1.425V max). The FPGA's IO voltage of the bank is 1.8V, so it should never exceed that level.

We originally assumed that our SYSREF was going to be a clock, so that's why we thought AC coupled would work. Now that we are using a single pulse for SYSREF, we are thinking of removing (shorting) the AC coupling caps.

Do you think the above will work? If not, let us know your recommendations.

Also, what is the common mode range for SYSREF input? The datasheet just lists 0.5V as typical.

thanks,
Scott

0 Kang Hsia over 8 years ago in reply to Scott Greeley1

TI__Guru 66184 points

Hi Scott,

For your system, do you have multiple DAC37J82's that requires multiple device latency synchronization? If both the absolute and relative latency is not a concern, then you could consider keeping the AC coupling approach and increase the number of sysref pulses. The idea is that after certain pulses the waveform will settle. You will need to make sure the AC coupling cap values are not significant enough to increase the charge time dramatically.

The SYSREF input has the same receiver architecture as the DACCLK input. It is weakly self-biased at 0.5V.

-Kang

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DAC37J82 register settings