This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC12D1600QML-SP - Interleave operation with multi devices in DES mode

Other Parts Discussed in Thread: ADC12D1600QML-SP

Hello,

My customer have some questions about ADC12D1600QML-SP.

[Q1]

Is it possible to operate interleave with multi ADC12D1600QML-SP devices in DES mode ?

[Q2]

If Q1 is possible, Can it use AutoSync Feature ?

I think the answer is No, it can not because AutoSync relies on the Sampling Clock arriving to each ADC at the same time.

Is my understanding correct ?

[Q3]

If Q1 and Q2 are possible, Can it use DCLK Reset Feature ?

I think the answer is Yes.

Is my understanding correct ?

Best Regards,

Hiroshi Katsunaga

  • Hi Hiroshi,Do you know what sampling rate the customer wants?
    Interleaving two ADCs in DES mode can work. Also, the autosync feature could be used.
    The Aperature Delay (tAD) could be used adjust the sampling window of the second ADC.
    Note, that will be a lot of fine tuning of things like gain and full scale to get the two ADCs to match for best performance.
  • Hi Kirby,

    Thank you for your fast response.

    They said that they want to do the sampling rate highly as much as possible.

    Their input signal information is as follows.

    fc = several hundred MHz

    BW = over 1GHz

    I have additional 2 questions.

    [Q1]

    My understanding is as follows.

    • CLK+/- must arrive to each ADC at the same instant. (This is Autosync requirement)
    • The sampling window of the second ADC adjust the registers (0xC:Aperture Delay Coarse Adjust and 0xD:Aperture Delay Fine Adjust).
    • The routing for the RCLK does not have any stringent requirements because delay of RCLK can adjust the registers (0xE:Autosync).
    • For FCLK > 1GHz, it is recommended to drive RCLK externally.

    Is my understanding correct ?

    [Q2]

    My understanding for driving DESIQ mode with 2 chip interleave is as follows.

    • Total input impedance is 25ohm for driving DESIQ mode with 2 chip interleave. (I referred Figure 47 in D/S P.48) So choose 2:1 balun.

    Is my understanding correct ?

    Best Regards,

    Hiroshi Katsunaga

  • Hi Kirby,

    Thank you for your response.
    I understood it.

    Thank you for your support.

    Best Regards,
    Hiroshi Katsunaga