LM97600 EVB

Hi Leo

 

Please check with the customer and confirm the following.

 

1. They are using the EVM with internal clock selected.

2. They are following the EVM startup procedure described on page 27 of the User Guide. I am copying it here below:

 

Data Capturing

VERY IMPORTANT: Initializing the FPGA SERDES Receiver

When the board is first powered on and initialized, one additional step must be taken before capturing

ADC data. The FPGA SERDES receiver is configured, but the Sync Req button on the Settings tab must

be clicked one time to perform Byte and Channel alignment. After this procedure is done the ByteAlign

and ChanAlign status information should be all ones.

In addition, when switching between Internal and External clocking, and/or changing the frequency of the

external clock, it is necessary to first enter the new ADC clock frequency in the entry field. This action will

cause the MGTREFCLK to be recalculated. This is the frequency that must be applied to the FPGA

REF_CLK inputs and is 1/12.5 the frequency of the ADC clock applied. Once the proper clock

frequencies are applied, click the Reconfig PLL and DRP button followed by the Sync Req button. These

actions reconfigure the GTX receivers in the FPGA for the new data rate. After this procedure is done the

ByteAlign and ChanAlign status information should be all ones as shown in the example above. If 0s are

present, then some lanes have failed Byte or Channel alignment, and the ADC data captured by the

FPGA will not be valid.

When switching back to Internal Clock, change the selection to Internal Clock, then click the Reconfig

PLL and DRP button followed by the Sync Req button. At that point the External Clock signal generator

should be disconnected or switched off to prevent performance degradation.

The board is now ready for a data capture. Before proceeding, perform a manual calibration of the ADC.

Even though the ADC performs a self-calibration at the time of power-up, it is recommended that the

user perform another calibration after sufficient time has passed for the system (primarily temperature) to

stabilize. Manual calibration is performed by clicking the Calibration via SPI button in the Register control

panel, Settings sub-tab.

Once this is done, capture a single acquisition by clicking the Acquire Data button(Item 5 in Figure 6).

This will capture and display a time domain acquisition in the main plot window.

 

Please let me know if they have been doing this or not and if adding these steps helps.

 

Best regards,

Jim B

 

Dear Jim,

customer feedback that they are testing with internal clock, but they don't find the button mentioned in the description on PC software,
could you please help to advise if any more detailed guild on this?

b/r
vincent

here is the picture i got from customer just now:

Can you share a screenshot of the whole Registers tab showing the results of the Sync Req operation?

There are three lines of information:

Lane: 9|8|7|6|5|4|3|2|1|0

ByteAlign:xxxxxxxxxxxxx

ChanAlign:xxxxxxxxxxxx

I want to know what values are there to the right of ByteAlign and ChanAlign. They must be all 1s to work properly.

Thanks,

Jim B

Hi Jim,
customer told me they all used default setting to process the test.
customer felt it should work fine with all default configure.
b/r
vincent

Hi vincent

It doesn't matter if they are using default settings or not. If they haven't done the last startup step of clicking the Sync Req button and seeing that all of the status bits change from 0 to 1, they will not get a valid data capture.

If the ByteAlign and ChanAlign status bits are all 1's then the data captured should be valid. In that condition they should then click the Calibration via SPI button to calibrate the ADC for optimal performance.

Please confirm these steps are being followed, and have them provide a screen shot of the entire Registers\Settings panel after doing the Sync Req. It should look like that shown in the image from the User Guide below. (In this case the input signal is a sine wave so the captured data is as expected).

Also please check to see if they have anything connected to the EVM signal inputs for these initial tests.

Best regards,

Jim B

Hi Jim,

thanks for you support.

it's going well at customer side according to your guide.

and one more question from customer:

customer want to know what will do on PC software side with those four button function:

1. Reconfig PLL and DRP

2. Calibration via SPI

3. Sync Req

4. Read Byte/Align Status

Hi Laisan

The button functions are as follows:

Reconfig PLL and DRP(1) - This button reconfigures the FPGA high speed serial data capture logic. This button must be clicked when the board is initially connected/powered up, and whenever the clock source is changed, or the external clock frequency is changed.

After clicking this button, the Sync Req(3) button must also be clicked, which triggers a re-synchonization sequence of the serial data link with the ADC.

After pressing the Sync Req button the ByteAlign and ChanAlign status will update.

To force a status check without triggering the re-synchronization sequence the Read Byte/Align Status(4) button can be clicked.

The Calibration via SPI(3) button sends serial commands to the ADC (a 0 to 1 transition of Register 02h, Bit 15 is required) to trigger the built-in self-calibration process. This should be done after the device temperature stabilizes, and after any change to clock source, clock frequency, or operating mode (# of channel inputs, etc.)

For more information please refer to this updated version of the LM97600RB User Guide:

/cfs-file/__key/communityserver-discussions-components-files/73/3173.LM97600RB-Users-Guide-rev3.pdf

Best regards,

Jim B