Hello,
My customer needs your help.
<The Issue>
The running disparity error occurred in their Xilinx FPGA on their board in the following case.
1. When they turned off the signal input.
2. When they pull the signal input cable.
3. When they gradually reduce the input signal level.
<Their configuration>
* fs = 2.8GSPS
* Bypass Mode
* Disabled the Scrambler
* K = 4
* AC Coupled Continuous SYSREF
* Differential SYNC
* The setting of the registers as follows.
0x0021 0x01 // De-assert reset
0x0021 0x00 // Initiate reset of all registers
0x0030 0x00 // SYSREF receiver and processor off
0x0040 0x04 // Set serializer pre-emphasis for high speed PCB
0x0066 0x03 // Foreground calibration mode with timing optimization enabled
0x002B 0x13 // Change reserved register to proper setting
0x0208 0x07 // Change over-range processing to longest interval
0x0051 0x84 // Calibration optimized for large signals
0x0201 0x0E // JESD_EN = 0 Scrambler disabled (default) K=4
0x0200 0x20 // Signed 2s complement Final filter has 0-dB gain Bypass mode
0x0202 0x40 // P54 PLL off, Differntial SYNC, Normal data mode
0x0030 0xC0 // SYSREF Receiver and processor on
0x0201 0x0F // JESD_EN = 1 Scrambler disabled (default) K=4
0x0050 0x0E // Initiate a forground calibration
[Q]
Is there any point to notice ?
Is there other necessary information ?
Best Regards,
Hiroshi Katsunaga
